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Pin No.
Pin Name
Signal Name
Pull Up/
Pull Dn
Type
Description
Bidirectional Centronics
64
CWOE
∗
CWOE
O
Centronics Write Output Enable: Controls the Output Enable signal of the
data register -from the peripheral to the host.
data register -from the peripheral to the host.
59
CROE
∗
CROE
O
Centronics Read Output Enable: Controls the OE of the Centronics
external register in the direction from the host to the peripheral (to the
IODATA(7:0) bus).
external register in the direction from the host to the peripheral (to the
IODATA(7:0) bus).
58
CWSTROBE
CWSTROBE
O
Centronics Write Strobe: Clocks data from the IODATA(7-0) into the
Centronics register (from peripheral to host).
Centronics register (from peripheral to host).
53
CRSTROBE
CRSTROBE
O
Centronics Read Strobe: Clocks data from the host into the Centronics
register (from host to peripheral).
register (from host to peripheral).
52
CSTROBE
∗
PALSTROBE
P.U.
I
Centronics Strobe signal
65
CACK
∗
CENTACK
O
Centronics acknowledge signal
54
CBUSY
CENTBUSY
O
Centronics Busy signal
62
CPERROR
CENTPERROR
O
Centronics Printer Error signal
63
CSELECT
CENTSELECT
O
Centronics Select signal
61
CAUTOFD
∗
PALAUTOFD
P.U.
I
Centronics Autofeed signal
51
CINIT
∗
N9
CENTINIT
CENTINIT
P.U.
I
Centronics Initialize signal
66
CFAULT
∗
CENTFAULT
O
Centronics Fault signal
50
CSELECTIN
∗
PALSELIN
P.U.
I
Centronics Select Input signal
Parallel Port Control
68
PSTROBE
∗
N.C.
O
Parallel Strobe: Clocks 8-bit or 16-bit parallel data from IODATA[15:0]
67
POE
∗
N.C.
O
Parallel Output Enable: When active (LOW), it controls the output enable
of a data buffer for 8-bit or 16-bit wide parallel data into IODATA[15:0]
of a data buffer for 8-bit or 16-bit wide parallel data into IODATA[15:0]
Video Control
137
VCLKIN
VCLGIO
P.U.
I
Video Clock In: Used for generating the video clock VCLK which is the
video data clock. The VCLKIN frequency is either VCLK
video data clock. The VCLKIN frequency is either VCLK
×
8 or VCLK.
138
VDATA
VDATA
O
Video Data: to the printer.
135
LINESYNC
∗
HSYNCGIO
P.U.
I
Line Synchronization: Input from the printer that indicates the beginning
of a line. In some printers this is called Beam Detect (BD) or SYNCBD
of a line. In some printers this is called Beam Detect (BD) or SYNCBD
∗
.
NOTE: LINESYNC
∗
is an edge-sensitive signal. It is clocked into the
3710/40 by the internal signal VCLK, where VCLK is equal to VCLKIN/8
when the PLL is used, and VCLKIN when the PLL is bypassed.
when the PLL is used, and VCLKIN when the PLL is bypassed.
136
PAGESYNC
∗
PSYNCGIO
P.U.
I
Page Synchronization: Input from the printer that indicates the beginning
of the page.
of the page.
VSYNC2
NOTE: PAGESYNC
∗
is an edge-sensitive signal. It is clocked into the
3710/40 by the internal signal VCLK, where VCLK is equal to VCLKIN/8
when the PLL is used, and VCLKIN when the PLL is bypassed.
when the PLL is used, and VCLKIN when the PLL is bypassed.
Misc.
160
TEST
GND FIXED
P.D.
I
Master Output Enable: When TEST is HIGH and RESET
∗
is active, All the
device outputs and I/Os are tri-stated.
29
RESET
∗
RESETO
I
Reset: Active low-will reset the GT-32011 to the initial state.
VDD
+5V (+/–5%)
VSS
Ground
NOTE: Pull Up/Pull Dn designates those pins with internal Pull Up (P.U.) or Pull Down (P.D.) resistors
– 31 –
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