AR-BD14 (serv.man5). ARBD14-Service Manual - Sharp Copying Equipment Service Manual (repair manual). Page 31

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Pin Assignment Table
Pin No.
Pin Name
Signal Name
Pull Up/
Pull Dn
Type
Description
CPU Interface
  1:  5
  8: 17
139:142
144:149
152:158
A/D[31:0]
A/D[0:31]
P.U.
I/O
Address/Date: Multiplexed address and data bus.
In the Address phase: A/D[31:4] are address, A/D[3:0] are Byte
Enable[3:0]. During Coprocessor Master cycles, A/D[3:2] contain address
bits 3 and 2, and not Byte Enables.
22, 23
ADDR[3:2]
ADDR[3:2]
P.U.
I/O
Non Multiplexed Address: Connected to the CPU ADDR[3:2]. In DMA
cycles the GT-32011 drives these lines.
21
BURST
BURST
P.U.
I/O
Burst Transfer: Used only during read cycles, the BURST signal indicates
that the current bus read is requesting a block of four continuous words
from memory. The pin connects to the CPU’s BURST/WRNEAR
 signal. In
DMA cycles the GT-32011 drives this signal HIGH.
24
ALE
ALE
P.D.
I/O
Address Latch Enable: Used by the CPU to indicate that the A/D bus
contains valid address information for the bus transaction. During
Coprocessor DMA cycles, the GT-32011 asserts ALE to capture the
address supplied by the Coprocessor.
5:6
SYSCLK
SYSCLK
I
System Clock: Connected directly to the CPU SYSCLK
 output.
25
RD
RD
P.U.
I/O
Read: Indicates a read access by the CPU. In DMA cycles the GT-32011
drivers the signal HIGH.
26
WR
WR
P.U.
I/O
Write: Indicates a write access by the CPU or the Coprocessor. In a non-
Coprocessor DMA cycle the GT-32011 drivers this signal HIGH.
30
ACK
ACK
O
Acknowledge: Indicates that the memory system has sufficiently
processed the bus transaction i.e. that the CPU may either terminate a
write cycle or process read data.
31
RDCEN
RDCEN
O
Read Buffer Clock Enable: Indicates to the CPU that there is valid data on
the A/D bus.
32
BUSREQ
BUREQ
O
Bus Request: The GT-32011 requests the CPU bus which is required for
I/O and Coprocessor DMA’s.
28
BUSGNT
BUSGNT
I
Bus Grand: Indicates that the CPU has relinquished the bus.
33
INT
INT3710
O
Interrupt: "OR’s" the internal and external interrupt sources.
27
DATAEN
DATAEN
I/O
Data Enable: indicates the data phase in CPU read cycles. In DMA the
GT-32011 asserts DATAEN when the ROM/DRAM drives data onto
A/D[31:0].
ROM
129
132
133
ROMCS[2:0]
ROMCS[2:0]
O
ROM Chip Select: Select one of the 3 ROM banks. They can be connected
to the ROM’s Chip Select or Output Enable. ROMCS[2] is connected to the
boot ROM, with a starting physical address 0x1fc00000.
134
ROMOE
N.C.
O
ROM Output Enable: Asserted when there is an access to any of the ROM
banks. Used to output- enable the ROM data in systems where there is a
buffer between ROM and DRAM data bus; eg. when using an interleaved
ROM configuration.
DRAM
108:111
114:150
DADR[10:0]
DRAMAD[10:0]
O
DRAM Address: Multiplexed row and column address connected to the
DRAM address.
121:123
RAS[2:0]
RAS[2:1]
O
Row Address Select: Supports up to three banks of DRAM, connected to
the RAS inputs of the DRAMs.
124:127
CAS[3:0]
CAS[2:0]
O
Column Address Select: Connects a CAS to each of the four bytes in
every bank.
128
DWR
DRAMWE
O
DRAM Write: Connects to the write pin of each of the DRAMs.
Coprocessor/External Agent Interface
39
EBREQ
+5V FIXED
P.U.
I
Ext. Agent Bus Request: An Ext. Agent bus request to make system
resource access in master mode.
40
EBGNT
+5V FIXED
O
Ext. Agent Bus Grant: The GT-32011 asserts EBGNT
 to grant the CPU
bus to the Ext. Agent. Once the EBGNT
 is asserted, it remains so until
EBREQ
 is deasserted.
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