AR-BD14 (serv.man5). ARBD14-Service Manual - Sharp Copying Equipment Service Manual (repair manual). Page 36

For the expansion interface, one slot is provided to allow a network
card, enabling the network connection.

The LAN board will provide an interface that consists of a 16 bit data
bus accessing a maximum of 64 KBytes of shared memory and an
interrupt control register, 17 addressing bits, interrupt lines, and con-
trol lines.

Signal Description (Between ICU board and LAN I/F board)

Pin No.

Signal
Name

Direction

Description

21, 19, 18,
17, 37, 44,
42, 40, 38,
36, 34, 32,
30, 28, 26,

24, 49

A0 – A16

OUT

Address lines that are used to access
the shared memory space. A0 - least
significant bit. word only accesses to
shared memory.

35, 33, 31,
29, 27, 25,
23, 22, 14,
13, 11, 10,

9, 7, 6, 5

D0 – 15

IN/OUT

Bi-directional data lines carrying the
data for memory requests. These lines
are buffered on the LAN board. D0 -
least significant bit.

*

 Loading will not exceed 1 LS TTL

load.

39

RESET-

OUT

Reset line to LAN board. This line is
used by the printer to request a
hardware reset.
Active Low.

43

NETCS-

OUT

Printer chip select pins. These lines
are used by the printer to indicate a
valid address for a memory operation.
NETCS- will only be active to LAN
board accesses.
Active Low.

45

NETOE-

OUT

Printer output enable pin. This line is
used by the printer to indicate the
printer bus is available. This signal is
qualified by NETCS-
Active Low.

47

R/W-

OUT

Printer Read/Write line. This line is
used by the printer to indicate a read
or write cycle.
Write Active Low.

41

NETRDY-

IN

LAN board Ready line. LAN board will
set this line active on a access to the
LAN board. It will be used to hold off a
printer access to shared memory.
Active Low.

15

NETINT-

IN

Interrupt printer. This line indicates the
LAN board wants to interrupt the
printer. The LAN board will set this line
low if Bit 3 of the ICR register is a "0".
Active Low.

57

NETON-

OUT

Board plugged in line. A low on this
line signifies a LAN board is plugged
into the printer.
Active Low.

1, 2, 3, 58,

59, 60

VCC

+5V power lines. These lines provide a
continuous

8, 12, 16,

48, 52, 56

GND

Ground lines. These lines provide a
common reference for bus and control
signals and provide a return for the
+5V power lines.

Timing Specification

NETCS, NETOE-, R/W-, NETRDY-

These signals are used as control lines to read and write data to
the LAN board.

R/W- is set high or low to indicate a read (1) or write (0) cycle.
NETCS- is set low by the printer to signal a memory access is
required and the printer address is now valid.

The LAN board will set NETRDI- within 30nS of receiving NETCS-

Upon receiving a NETCS- the LAN board will begin memory ar-
bitration with the printer. NETRDY- will be deasserted when the
LAN board memory arbiter determines the bus is available.

MAXIMUM TIME BEFORE LAN BOARD COMPLETES THE
PRINTER ACCESS IS 530nS.

The printer will finish its memory access cycle by deasserting
NETCS- and NETOE-

Address and Data signals.

READ:

Address and R/W- will be valid before NETCS- is as-
serted. Data will be valid before NERDY is deasserted.

WRITE:

Address and RW- will be valid before CSPn- is as-
serted. Data will be valid for the duration of the CPSn-
signal.

Common Memory

A maximum of 64 KBytes will allocated for shared memory access.
Common memory will be allocated at LAN board locations 0000 thru
FFFF.

For control of I/O and peripheral circuits, the LZ95NA8: QFP100PIN
(1600 gate) is used. With this G/A, generating each I/O select signal,
image output control, flash write control are processed. For details of
this G/A signal line, refer to the table below.

Pin

No.

Signal

name

I/O

Functions

1

PCLK

IBFSA

Horizontal effective area clock

2

TCNTO

IBF

Test signal 0 for counter

3

A22

IBF

Address 22

4

IOWR-

IBF

I/O write signal from LZ95NA8

5

TEST-

IBF

Test signal (L: test mode)

6

BE2-

IBF

Byte enable signal 2

7

EDMAK-

IBF

DMA acknowledge signal

8

RAS1-

IBF

DRAM row address select signal 1
from LZ95NA8

9

BE3-

IBF

Byte enable signal 3

10

ED04

IBF

I/O data 4

11

RAS0-

IBF

DRAM row address select signal 0
from LZ95NA8

12

ED05

IBF

I/O data 5

13

GND

14

BE0-

IBF

Byte enable signal 0

15

PD1

IBF

DRAM module presence detect pin 1

16

PD0

IBF

DRAM module presence detect pin 0

17

RMCS0-

IBF

ROM chip select signal 0

18

SELI2-

IBF

Interruption select signal 2

19

A5

IBF

Address 5

20

N.C

21

BE1-

IBF

Byte enable signal 1

22

VSYNC-

IBF

Vertical sync signal

23

A4

IBF

Address 4

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