AR-BD14 (serv.man5). ARBD14-Service Manual - Sharp Copying Equipment Service Manual (repair manual). Page 29

Pin No

Pin name

Signal name

I/O

Description

46

ALE

ALE

I/O

Address Latch Enable: Used to indicate that the A/D bus contains valid address information
for the bus transaction. This signal is used by external logic to capture the address for the
transfer, typically using transparent latches.

During cache coherency operations, the R3081 monitors ALE at the start of a DMA write, to
capture the write target address for potential data cache invalidates.

45

Rd

RD

Read: An output which indicates that the current bus transaction is a read.

44

Wr

WR

I/O

Write: An output which indicates that the current bus transaction is a write. During coherent
DMA, this input indicates that the current transfer is a write.

43

DataEn

DATAEN

O

External Data Enable: This signal indicates that the A/D bus is no longer being driven by the
processor during read cycles, and thus the external memory system may enable the drivers
of the memory system onto this bus without having a bus conflict occur. During write cycles,
or when no bus transaction is occurring, this signal is negated, thus disabling the external
memory drivers.

53

Burst/WrNear

BURST

O

Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current
bus read is requesting a block of four contiguous words from memory. This signal is asserted
only in read cycles due to cache misses; it is asserted for all-Cache miss read cycles, and for
D-Cache miss read cycles if quad word refill is currently selected.

On write transactions, the WrNear output tells the external memory system that the bus
interface unit is performing back-to-back write transactions to an address within the same 512
word page as the prior write transaction. This signal is useful in memory systems which
employ page mode or static column DRAMs, and allows near writes to be retired quickly.

36

Ack

ACK

I

Acknowledge: An input which indicates to the device that the memory system has sufficient-
ly processed the bus transaction, and that the CPU may either terminate the write cycle or
process the read data from this read transfer.

During Coherent DMA, this input indicates that the current write transfer is completed, and
that the internal invalidation address counter should be incremented.

35

RdCEn

RDCEN

I

Read Buffer Clock Enable: An input which indicates to the device that the memory system
has placed valid data on the A/D bus, and that the processor may move the data into the
on-chip Read Buffer.

40

SysClk

SYSCLK

O

System Reference Clock: An output from the CPU which reflects the timing of the internal
processor "Sys" clock. This clock is used to control state transitions in the read buffer, write
buffer, memory controller, and bus interface unit. This clock will either be at the same
frequency as the CPU execution rate clock, or at one-half that frequency, as selected during
reset.

34

BusReq

BUSREQ

I

DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its
bus interface signal so that they may be driven by an external master.

39

BusGnt

BUSGNT

O

DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has
been detected, and that the bus is relinquished to the external master.

19

CohReq

+5V FIXED

I

Coherent DMA Request. An input used by the external DMA controller to indicate that the
requested DMA operations could involve hardware cache coherency. This signal is the
Rsvd(0) of the R3051.

28 29
33

SBrCond(3:2)
BrCond(0)

+5V FIXED

I

Branch Condition Port: These external signals are internally connected to the CPU signals
CpCond(3:0). These signals can be used by the branch on co-processor condition instruc-
tions as input ports. There are two types of Branch Condition inputs: the SBrCond inputs
have special internal logic to synchronize the inputs, and thus may be driven by
asynchronous agents. The direct Branch Condition inputs must be driven synchronously.
Note that BrCond(1) is used by the internal FPA, and thus is not available on an external pin.

37

BusError

+5V FIXED

I

Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external
bus error. This signal is only sampled during read and write operations. If the bus transaction
is a read operation, then the CPU will take a bus error exception.

20 23
 24

Int(5:3)

INT(5:3)

I

Processor Interrupt: During normal operation, these signals are logically the same as the
Int(5:0) Slnt(2:0) signals of the R3000. During processor reset, these signals perform mode
initialization of the CPU, but in a different (simpler) fashion than the interrupt signals of the
R3000.

There are two types of interrupt inputs: the Slnt inputs are internally synchronized by the
processor, and may be driven by an asynchronous external agent. The direct interrupt inputs
are not internally synchronized, and thus must be externally synchronized to the CPU. The
direct interrupt inputs have one cycle lower latency than the synchronized interrupts. Note
that the interrupt used by the on-chip FPA will not be monitored externally.

4

ClkIn

CLKIN

I

Master Clock Input: This input clock can be provided at the execution frequency of the CPU
(1x clock mode) or at twice that frequency (2x clock mode), as selected at reset.

38

Reset

RESET0

I

Master Processor Reset: This signal initializes the CPU. Mode selection is performed during
the last cycle of Reset.

15:18

Rsvd(4:1)

N.C.

I/O

Not used

– 27 –