Read Sharp AR-BD14 (serv.man5) Service Manual online
Pin No.
Pin Name
Signal Name
Pull Up/
Pull Dn
Type
Description
41
EAS
∗
+5V FIXED
P.U.
I/O
Ext. Agent Address Strobe:
Master Mode – The external agent indicates that it drives valid data on the
A/D bus.
A/D bus.
Slave mode – The GT-32011 indicates that it drives valid data on the A/D
bus.
bus.
42
EDS
∗
+5V FIXED
O
Ext. Agent Data Strobe:
Master mode – during Write indicates that there is valid data on the A/D
bus. During Read indicates a request for data.
bus. During Read indicates a request for data.
Slave mode – the GT-32011 drives EDS
∗
to indicate that it is ready to
accept data during reads or that valid data is available during writes ont he
A/D bus.
A/D bus.
37
EDTACK
∗
+5V FIXED
P.U.
I/O
Ext. Agent Data acknowledge:
Master mode – The GT-32011 asserts EDTACK
∗
to indicate that it is
receiving or driving the requested data to/from the A/D bus.
Slave mode – The Ext. Agent asserts EDTACK
∗
to signal that it has
supplied or received data on its bus.
43
EAACK
∗
+5V FIXED
O
Ext. Agent Address Acknowledge: The GT-32011 asserts EAACK
∗
one
clock after asserting ALE for the Ext. Agent. This insures that the Ext. Agent
continues driving the address until latched by the system.
continues driving the address until latched by the system.
42
ECS
∗
+5V FIXED
O
Ext. Agent Chip Select: When the CPU accesses the Ext. Agent, the
GT-32011 asserts ECS
GT-32011 asserts ECS
∗
. It is active one clock before GT-32011 asserts
EAS
∗
.
34
EADOE
∗
+5V FIXED
O
Ext. Agent A/D Output Enable: The GT-32011 asserts EADOE
∗
when the
Ext. Agent drives the address to the A/D bus, and in the data phases of the
Ext. Agent.
Ext. Agent.
35
EADDIR
∗
+5V FIXED
O
Ext. Agent A/D Direction: The GT-32011 asserts EADDIR
∗
(LOW) when
the Ext. Agent drives the A/D bus.
36
EATOE
∗
+5V FIXED
O
Ext. Agent Address To Output Enable: The GT-32011 asserts EATOE
∗
in the address phase of cycles in which the CPU accesses the Ext. Agent.
Buffer Control
159
OEMAD
∗
OEMAD
O
Output Enable between Memory and A/D: Output enable for the data
path transceiver, between the memory system and the A/D bus.
path transceiver, between the memory system and the A/D bus.
I/O Bus
89:100
104:107
104:107
IODATA[15:0]
IODATA[15:0]
P.U.
I/O
Input/Output Data: Bidirectional 16-bit I/O Data bus.
79
IORD
∗
IORD
O
Input/Output Read: Active during Read from an I/O device.
78
IOWR
∗
IOWR
O
Input/Output Write: Active during Write to an I/O device.
85, 86
IOCS[1:0]
∗
IOCS[1:0]
O
Input/Output Chip Selects: Chip selects for 8 bit I/O channels 0 and 1.
83, 84
IOGPCS[1:0]
∗
IOGPCS[1:0]
O
Input/Output Chip Selects: Chip select outputs for 16 bit I/O channels 0
and 1.
and 1.
87, 88
DMAREQ[1:0]
DMAREQ[1:0]
P.D.
I
DMA Request: Requesting DMA service on channels 0 and 1.
76, 77
DMAACK
∗
[1:0]
∗
DMAACK[1:0]
O
DMA acknowledge: Indicating that DMA access is granted on channels 0
and 1.
and 1.
80
IOA1
N.C.
O
Input/Output Address bit 1: Provides a half word (16 bit) address on the
I/O bus.
I/O bus.
81, 82
IOBE[1:0]
∗
N.C.
O
Input/Output Byte Enable: Indicates which byte data bus is valid on the 16
bit I/O bus.
bit I/O bus.
75
IOWAIT
∗
IOWAIT
P.U.
I
Input/Output Wait: Indicates to the GT-32011 that a transfer cycle on the
I/O bus needs to be extended.
I/O bus needs to be extended.
44
PIO0
IDREQ
P.U.
I/O
Input data request signal to I/O and peripheral controller
45
PIO1
ODREQ
P.U.
I/O
Output data request signal to I/O and peripheral controller
46
PIO2
EINTR11
P.U.
I/O
Interrupt signal from NIC Board
47
PIO3
EINTR12
P.U.
I/O
Interrupt signal from NIC Board
48
PIO4
SONIC_INT
P.U.
I/O
Interrupt signal from NIC Board
49
PIO5
PSYNCG10
P.U.
I/O
Vertical sync signal
– 30 –
Click on the first or last page to see other AR-BD14 (serv.man5) service manuals if exist.