Read Sharp AR-BD14 (serv.man5) Service Manual online
(2) General
The printer unit is composed of the printer PWB, the Centronics
connector PWB, and network I/F PWB, and the interface harness
which connects them.
connector PWB, and network I/F PWB, and the interface harness
which connects them.
The component sections of the printer PWB are described below.
A. CPU section
<CPU : R3081>
The CPU section of the printer controller is composed of two chips
which include the high-speed RICS microprocessor IDT79R3081 with
the cache memory and the peripheral circuits (for memory control,
image print control, various I/O control). The CPU’s operating fre-
quency is 50MHz, and the system clock is 25MHz.
which include the high-speed RICS microprocessor IDT79R3081 with
the cache memory and the peripheral circuits (for memory control,
image print control, various I/O control). The CPU’s operating fre-
quency is 50MHz, and the system clock is 25MHz.
Pin configurations
Pin description
Vss
Vcc
Vcc
Clkln
Rsvd(4)
Rsvd(3)
Rsvd(2)
Rsvd(1)
Rsvd(1)
CohReq
Int(5)
Vss
Vcc
Int(4)
Int(3)
Int(3)
SInt(2)
SInt(1)
SInt(0)
SInt(0)
SBrCond(3)
SBrCond(2)
SBrCond(2)
NC
Vss
Vcc
12
Vss
Vcc
A/D(14)
A/D(13)
Vcc
A/D(14)
A/D(13)
A/D(12)
A/D(11)
A/D(10)
A/D(10)
A/D(9)
Vcc
Vss
Vss
A/D(8)
A/D(7)
A/D(6)
A/D(6)
A/D(5)
A/D(4)
A/D(3)
Vss
Vcc
A/D(3)
Vss
Vcc
A/D(2)
A/D(1)
A/D(1)
A/D(0)
54
33
1 84
75
84-Pin MQUAD/PLCC
Top View
Pin No
Pin name
Signal name
I/O
Description
54:56
59:64
67:72
75:80
83:84
1: 4
7:11
59:64
67:72
75:80
83:84
1: 4
7:11
A/D(31:0)
A/D(31:0)
I/O
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus
transaction in one phase, and which is used to transmit data between the CPU and external
memory resources during the rest of the transfer.
transaction in one phase, and which is used to transmit data between the CPU and external
memory resources during the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase,
information about the transfer is presented to the memory system to be captured using the
ALE output. This information consists of:
information about the transfer is presented to the memory system to be captured using the
ALE output. This information consists of:
Address(31:4):
The high-order address for the transfer is presented on A/D(31:4).
BE(3:0):
These strobes indicate which bytes of the 32-bit bus will be involved
in the transfer, and are presented on A/D(3:0).
in the transfer, and are presented on A/D(3:0).
During write cycles, the bus contains the data to be stored and is driven from the internal
write buffer. On read cycles, the bus receives the data from the external resource, in either a
single data transaction or in a burst of four words, and places it into the on-chip read buffer.
write buffer. On read cycles, the bus receives the data from the external resource, in either a
single data transaction or in a burst of four words, and places it into the on-chip read buffer.
During cache coherency operations, the R3081 monitors the A/D bus at the start of a DMA
write to capture the write target address for potential data cache invalidates.
write to capture the write target address for potential data cache invalidates.
51
52
52
Addr(3:2)
ADDR(2:3)
O
Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the
processor. Specifically, this two bit bus presents either the address bits for the single word to
be transferred (writes or single datum reads) or functions as a two bit counter starting at ‘00’
for burst read operations.
processor. Specifically, this two bit bus presents either the address bits for the single word to
be transferred (writes or single datum reads) or functions as a two bit counter starting at ‘00’
for burst read operations.
During cache coherency operations, the R3081 monitors the Addr bus at the start of a DMA
write to capture the write target address for potential data cache invalidates.
write to capture the write target address for potential data cache invalidates.
48
Diag(1)
N.C.
O
Not used
47
Diag(0)/
Ivd Req
Ivd Req
LAST
I/O
Diagnostic Pin 0. This output distinguishes cache misses due to instruction references from
those due to data references, and presents the remaining bit of the miss address. The value
output on this pin is also time multiplexed:
those due to data references, and presents the remaining bit of the miss address. The value
output on this pin is also time multiplexed:
I/D:
If the "Cached" Pin indicates a cache miss, then a high on this pin at
this time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an un-
cached reference, then this pin is undefined during this phase.
this time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an un-
cached reference, then this pin is undefined during this phase.
Miss Address (2): During the remainder of the read operation, this output presents ad-
dress bit (2) of the address the processor was attempting to reference
when the cache miss occurred. Regardless of whether a cache miss
is being processed, this pin reports the transfer address during this
time.
when the cache miss occurred. Regardless of whether a cache miss
is being processed, this pin reports the transfer address during this
time.
During write cycles, the value of this pin during both the address and data phases is
reserved.
reserved.
Invalidate Request. An input provided by an external DMA controller to request that the CPU
invalidate the Data Cache line corresponding to the current DMA write target address.
invalidate the Data Cache line corresponding to the current DMA write target address.
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