Read Sharp AR-BD14 (serv.man5) Service Manual online
[9] ELECTRICAL SECTION
(1) Block diagram
A. Basic Specifications
CPU:
IDT79R3081/50MHz
32bit microcontroller (below functions include)
MIPS R3000-core, 16KB INST, 4KB Data cache,
MMU,
MMU,
FPA (R3010A compatible)
Frequency = 50MHz (System clock = 25MHz)
Package = 84pin PLCC
ASIC:
GT-32011
DRAM controller (Max 40Mbyte area, 3 banks)
ROM controller (Max 20Mbyte area, 3 banks)
Video controller, Centronics controller,
Interrupt controller, General purpose I/O (6 port)
DMA counter 2ch. + 1ch for Centronics
24bit timer/counter, Package = 160pin PQFP
ASIC:
R3741A
P1284 Enhancement ASIC
EPLD Version (ALTERA EMP7064-15)
ASIC:
D9001-MF
EET, Toner save
Gate Array:
LZ95NA8
About 1000 gates
Memory:
Base ROM:
1MB max. Device = 256k
×
16bit,2pcs
4Mbit EPROM: HN27C4096G-10
Flash ROM:
8MB max. Device = 1M
×
16bit ,4pcs
16Mbit Flash: LH28F016SUT-10
Base DRAM:
16MB max. Device = 4M
×
4bit ,8pcs
16Mbit DRAM:uPD4217400 (Fast Page Mode)
NVRAM:
8K byte
Dallas DS1643-15
Nonvolatile Timekeeping RAM
package = 28pin DIP
Expansion
Memory:
Memory:
SIMM DRAM (Option)
Available in 16MB
72pin access time 60nsec
None parity
Peripherals:
Engine I/F
*
Serial I/F for command and status
*
Video I/F
Parallel I/F
*
IEEE-P1284
External I/O
*
LAN Card
Serial I/F
*
for only debug
Fl
as
h R
h R
O
M
E
x
te
nd
ed
R
O
ed
R
O
M
A
re
a
Ma
x
8
M
B
E
x
te
n
ded D
R
A
M A
rea
32bit Add.
bus
32bit Data
bus
32b
it Loc
al
B
u
s
16bit I/O Bus
GT-32011
8bit I/O Bus
NVRAM
8KB
R3741A
Bi-Parallel I/F
(IEEE1284)
Ho
s
s
t-
P
C
SW3
LED0~3
M
a
x202
De
bu
g CN
bu
g CN
RS-232C I/F
IC
U CN
Engine I/F
T
D
62
50
4
50
4
Ch-A
Ch-B
CPU
IDT79R3081
50MHz
OSC
50MHz
Add.Latch
373
ROM
1MB
DRAM
16MB
Data Buff.
245
LZ95NA8
G/A
QFP 100pin
S
e
rial
2c
h
h
ESC
C
A
M
D8
5C
30
5C
30
EET
D
9
001M
F
OSC
58.465MHz
Misc.
I/O
Logic
C
entr
o
Logi
c
ID
T29FC
T
52
B
B
T
LS
24
5,
24
5,
24
4
4
Centro
CN
External
CN1
Network
Card
(Option)
ASIC
ASIC
Not used in the
field service
field service
– 25 –
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