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Pin
Number
Pin Symbol
Pin
Type
Description
52, 47
DCD1,
DCD2
DCD2
I
Data Carrier Detect. When
low, this input indicates that
the data carrier has been
detected by the modem or
data set. The DCD signal is a
modem status input whose
condition can be tested by the
CPU by reading bit 7 (DCD)
of the MSR. Bit 7 is the
complement of the DCD
signal. Bit 3 (DDCD) of the
MSR indicates whether DCD
has changed state since the
previous reading of the MSR.
Whenever the DCD bit of the
MSR changes state, an
interrupt is generated if the
modem status interrupt is
enabled. DCD has no effect
on the receiver.
low, this input indicates that
the data carrier has been
detected by the modem or
data set. The DCD signal is a
modem status input whose
condition can be tested by the
CPU by reading bit 7 (DCD)
of the MSR. Bit 7 is the
complement of the DCD
signal. Bit 3 (DDCD) of the
MSR indicates whether DCD
has changed state since the
previous reading of the MSR.
Whenever the DCD bit of the
MSR changes state, an
interrupt is generated if the
modem status interrupt is
enabled. DCD has no effect
on the receiver.
91
DIR
O
Direction. This high drive
open drain output determines
the direction of the head
movement (low = step in, high
= step out). When in the write
or read modes, this output is
high.
open drain output determines
the direction of the head
movement (low = step in, high
= step out). When in the write
or read modes, this output is
high.
93, 92
DR0, DR1
O
Drive. These high drive open
drain outputs are drive select
signals for drives 0 and 1.
They are ANDed with the
corresponding motor enable
lines. These pins contain
encoded drive select
information if bit 7 of the
configuration register is set.
drain outputs are drive select
signals for drives 0 and 1.
They are ANDed with the
corresponding motor enable
lines. These pins contain
encoded drive select
information if bit 7 of the
configuration register is set.
69
DRQ
O
DMA Request. This is an
active high output that signals
the DMA controller that a data
transfer is needed. It is
enabled when D3 of the drive
control register is set. The
SPECIFY command must be
used to enable the DMA
mode.
active high output that signals
the DMA controller that a data
transfer is needed. It is
enabled when D3 of the drive
control register is set. The
SPECIFY command must be
used to enable the DMA
mode.
84
DRVTYP
I
Drive Type. This input is
used by the controller to
enable the 300 kb/s mode. It
enables the use of flexible
drives with either dual or
single-speed spindle motors.
This pin is tied low for dual-
speed motors and tied high
for single-speed motors
(standard AT drives). When
this pin is low, and 300 kb/s
data rate is selected in the
data rate register, the PLL
(phase locked loop) actually
uses 250 kb/s. When high
and 300 kb/s is selected, 300
kb/s is used.
used by the controller to
enable the 300 kb/s mode. It
enables the use of flexible
drives with either dual or
single-speed spindle motors.
This pin is tied low for dual-
speed motors and tied high
for single-speed motors
(standard AT drives). When
this pin is low, and 300 kb/s
data rate is selected in the
data rate register, the PLL
(phase locked loop) actually
uses 250 kb/s. When high
and 300 kb/s is selected, 300
kb/s is used.
Pin
Number
Pin Symbol
Pin
Type
Description
73
DSKCHG/RG
I
Disk Change/Read Gate.
This disk interface input
indicates when the disk drive
door has been opened. The
active high state of this input
is read from bit D7 of address
3F7h. When RG bit in the
mode command is set, this
pin functions as a read gate
signal. When low, it forces the
data separator to lock to the
crystal, and when high it locks
to the data for diagnostic
purposes.
This disk interface input
indicates when the disk drive
door has been opened. The
active high state of this input
is read from bit D7 of address
3F7h. When RG bit in the
mode command is set, this
pin functions as a read gate
signal. When low, it forces the
data separator to lock to the
crystal, and when high it locks
to the data for diagnostic
purposes.
53, 46
DSR1,
DSR2
DSR2
I
Data Set Ready. When low,
this input indicates that the
modem or data set is ready to
establish the communications
link with UART. DSR signal is
a modem status input whose
condition can be tested by the
CPU by reading bit 5 (DSR) of
the MSR. Bit 5 is the
complement of DSR. Bit 1
(DDSR) of the MSR shows
whether DSR has changed
state since the previous
reading of the MSR. When
the DSR bit of the MSR
changes its state, and
interrupt is generated if the
MODEM Status Interrupt is
enabled.
this input indicates that the
modem or data set is ready to
establish the communications
link with UART. DSR signal is
a modem status input whose
condition can be tested by the
CPU by reading bit 5 (DSR) of
the MSR. Bit 5 is the
complement of DSR. Bit 1
(DDSR) of the MSR shows
whether DSR has changed
state since the previous
reading of the MSR. When
the DSR bit of the MSR
changes its state, and
interrupt is generated if the
MODEM Status Interrupt is
enabled.
54, 44
DTR1,
DTR2
DTR2
O
Data Terminal Ready. When
low, this output informs the
modem or data set that the
UART is ready to begin a
communications link. DTR
can be set to an active low by
programming bit 0 (DTR) of
the modem control register
(MCR) to a high level. A
master reset operation sets
this signal to its inactive (high)
state. When the XTSEL pin is
high during reset, the loop
mode operation retains this
signal at its inactive state.
When the XTSEL pin is low
during reset, the associated
pin state is controlled by bit 0
of the MCR during loop mode
operation.
low, this output informs the
modem or data set that the
UART is ready to begin a
communications link. DTR
can be set to an active low by
programming bit 0 (DTR) of
the modem control register
(MCR) to a high level. A
master reset operation sets
this signal to its inactive (high)
state. When the XTSEL pin is
high during reset, the loop
mode operation retains this
signal at its inactive state.
When the XTSEL pin is low
during reset, the associated
pin state is controlled by bit 0
of the MCR during loop mode
operation.
28
ERR
I
Error. This input is set low by
the printer when it has
detected an error.
the printer when it has
detected an error.
82
FILTER
I/O
Filter. This pin is the output of
the charge pump and the
input to the VCO. One or
more filters are attached
between this pin and the
FGND250, FGND500, and
VSSA pins.
the charge pump and the
input to the VCO. One or
more filters are attached
between this pin and the
FGND250, FGND500, and
VSSA pins.
– 6 –
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