ER-A850 (serv.man3). ERA8RS RS232 Interface Service Manual - Sharp EPOS Service Manual (repair manual). Page 10

Pin

Number

Pin Symbol

Pin

Type

Description

85

SETCUR

O

Set Current. An external
resistor connected from this
pin to analog ground
programs the amount of
charge pump current that
drives the external filters. This
PLL Filter Design section
shows how to determine the
values.

56, 42

SIN1, SIN2

I

Serial Input. This input
receives composite serial
data from the
communications link
(peripheral device, modem, or
data set).

29

SLCT

I

Select. This input is set high
by the printer when the printer
is selected.

37

SLIN

O

Select Input. This output
selects the printer when the
signal is low.

57, 41

SOUT1,
SOUT2

O

Serial Output. This output
sends composite serial data
output to the communications
link (peripheral, modem or
data set). The SOUT signal is
set to the marking (logic 1)
state upon a master reset
operation.

33

STB

O

Data Strobe. This output
indicates to the peripheral that
data at the parallel port is
valid.

87

STEP

O

Step. This open drain high
drive output produces a pulse
at a software programmable
rate to move the head during
a seek operation.

71

TC

I

Terminal Count. This active
high input indicates the end of
a DMA transfer. This signal is
enabled when the DMA
acknowledge pin is active.

97

TRK0

I

Track 0. This active low input
tells the controller that the
head is at track zero of the
selected disk drive.

81, 74,
45, 34

VDD, A, B,
C, D

+5V Power. This is the power
supplied to the FDC analog,
FDC digital, serial ports, and
parallel port circuitry,
respectively.

77, 100,
65, 59,
27, 89

VSS A, B, C,
D, E, F

0V Reference. This is the
reference voltage for the
FDC, analog, FDC digital,
CPU interface, serial ports,
parallel port, and disk
interface output drive circuitry,
respectively.

90

WDATA

O

Write Data. This high drive
open drain output is a write
pre-compensated serial data
to be written onto the selected
disk drive.

Pin

Number

Pin Symbol

Pin

Type

Description

86

WGATE

O

Write Gate. This active low
open drain high drive output
enables the write circuitry of
the selected disk drive. This
signal has been designed to
prevent glitches during power
up and power down. This
prevents writing to the disk
when power is cycled.

99

WPROT

I

Write Protect. This input
indicates that the disk is write
protected. When a disk is
write protected, any
command that writes to it is
inhibited.

14

WR

I

Write. When this input is low
while the chip is selected,
CPU can write control words
or data into the selected
register.

18

XTSEL

I

XT Select. When this input is
low during reset, the chip
operates in the XT compatible
mode. When high, it operates
in the AT compatible mode. A
pull down or pull up resistor
must always be attached to
this pin.

The following sections describe each of the M5105 major functional
blocks. Each functional block is described as independently of the
other blocks as possible. Software can address all blocks inde-
pendently of each other,, except for the configuration register and low
power mode operation. The configuration register affects all other
blocks by determining which ones the address decoder can activate.
The low power mode is enabled and disabled via the flexible disk
controller mode command. Enabling low power mode stops the 24
MHz crystal and clock oscillation to all logic blocks. Software should
ensure that both UARTs and the flexible disk controller are idle and
continue to be idle while the low power mode is enabled.

This decodes address signals A0 

∼

 A9 and qualifies them. If qualified,

it activates the appropriate function block. The XTSEL pin determines
whether function blocks respond to the industry standard XT or AT
address.

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