ER-A850 (serv.man3). ERA8RS RS232 Interface Service Manual - Sharp EPOS Service Manual (repair manual). Page 2

Board specifications

ISA 16 bit bus half size expansion board

Major device

ACER Super I/O M5105A4E

Interface

Serial
interface

RS-232 (D-sub 9pin) 

×

 2

Parallel
interface

Conforming to Centronics
standards (D-sub 25pin) 

×

 1

Hard disk

No (Reserved)

Floppy disk

No (Reserved)

Parts enclosed with dotted line are not installed in the product.

•

100% compatible with IBM PC, XT and AT architecture

•

100% compatible with the industry  standard 765A architecture.
Software compatible with the INS8250N-B, INS8250A and
NS16450 UARTs

•

Supports on-chip analog data separator operating up to 1 mb/s

•

Implements all DP8473 flexible disk controller functions.

•

Supports bidirectional parallel port for printer or scanner operation
and has all the standard Centronics and IBM PC, XT, and AT
interface signals

•

Provides decoding and chip selects for a fixed disk interface
(EHDI) and address decoding and strobe generation for a game
port

•

Integrates all PC XT and AT logic:

–

On-chip 24 MHz crystal oscillator
(maximum operating frequency is 24 MHz)

–

DMA enable logic

–

IBM-compatible address decode of A0 

∼

 A9

–

24 mA CPU bus interface buffers, 40 mA flexible drive interface
buffers

–

Data rage/drive control registers

•

Two-pin programmable precompensation modes

•

Adds or deletes standard asynchronous communication bits (start,
stop, and parity) to or from the serial data stream

•

High current drive capability for the parallel port

•

Modem control functions for each UART channel (CTS, RTS, DSR,
DTR, RI, and DCD)

•

Separate interrupt request lines for the parallel and serial ports.
Independently controlled transmit, receive, line status, and data set
interrupts

•

Programmable baud generators for each UART channel divide the
input clock by 1 to (2

16

 – 1) and generate the internal 16 X sample

clock

•

Precision analog data separator:

–

Self-calibrating PLL and delay line

–

Automatically chooses one of the three filters

–

Intelligent read algorithm

•

Fully programmable serial-interface characteristics:

–

5, 6, 7, or 8-bit characters

–

Even, odd, or no parity generation and detection

–

1, 1.5, or 2 stop bit generation

The Acer M5105 chip incorporates two full function universal asyn-
chronous receiver/transmitters (UARTs), a flexible disk controller
(FDC) with analog data separator, parallel port, game port decode,
fixed disk controller decode, standard XT/AT address decoding for
on-chip functions, and a configuration register. It offers a single-chip
solution to the most common IBM PC, XT, and AT peripherals.

The flexible disk controller is fully compatible with the industry stand-
ard 765A architecture. It includes more advanced options such as a
high-performance data separator, extended track range to 4096, im-
plied seek command, scan command, and supports both IBM and
ISO 3.5-inch formats. The UARTs are compatible with either the
INS8250N-B or the NS16450. The parallel port, fixed disk select, and
game port select logic maintain complete compatibility with the IBM
XT and AT. Hardware selects XT or AT compatibility. The configura-
tion register is one byte wide and can be programmed via hardware
or software. By controlling this register, the user can assign standard
AT addresses and disable any major on-chip function (e.g., the FDC,
either  UART, or the parallel port) independently of the others. This
allows for flexibility in system configuration when adapter boards con-
tain duplicate functions.

Fig. 1 M5105 Basic Configuration Diagram

ISA
BUS

LS245

PLD

Super I/O
M5105A4E

MAX211CAI

DR/
RCV

DR/
RCV

40pin HDD
     and
40pin HDD

D-Sub
9pin

RS-232

D-Sub
9pin

RS-232

D-Sub
25pin

Printer

34pin

FDD

Data bus

ADD bus

Control bus

Serial

Serial

Parallel

Floppy

GRD

GWR

SIN1

SOUT1

RTS1

DTR1

CTS1

DSR1

RI1

DCD1

HCS1

HCS0

P

UMP

/P

RE

N

DRV

T

Y

P

S

E

TCUR

SIN2

SOUT2

RTS2

DTR2

CTS2

DSR2

RI2

DCD2

RDATA

WDATA

WGATE

HDSEL

DIR

STEP

INDEX

TRK0

DSKCHG/RG

WRTPRT

PRM/LC

MTR0, 1

DRV0, 1

CRPE XTSEL CRB0~B7 P0E

SLIN

STB

AFD

INIT

ACK

ERR

PE

SLCT

BUSY

PD0~7

FGND500
FGND250

FILTER

24MHz

crystal

or clock

source

OSC1

OSC2

DAK

DRQ

TC

IRQ7

IRQ6

IRQ4

IRQ3

WR

RD

AEN

MR

A0~A9

D0~D7

A10~A15

decode

IOL

FDC

configuration

logic

Hard disk

interface

Gate

port

logic

EIA

drivers

EIA

drivers

Floppy disk

drive

connector

Parallel

port

direction

Configuration

select logic

Parallel port

connector

External

FDC

filter

Sy

s

tem

 bus

– 1 –