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Pin
Number
Pin Symbol
Pin
Type
Description
1
MR
I
Master Reset. When high,
this input clears all registers,
except the parallel port data
and status registers (UART
receiver buffer, transmitter
holding, divisor latch
registers). In the flexible disk
controller, it resets all disk
drive output lines to their
disabled state. Reset clears
the drive control register, sets
the data rate register to 250
kb/s, and sets the main status
register to 80. The mode
register default values are
given in the mode register
description. To prevent
glitches from activating the
reset sequence, attach a
1000 pF capacitor to this pin.
this input clears all registers,
except the parallel port data
and status registers (UART
receiver buffer, transmitter
holding, divisor latch
registers). In the flexible disk
controller, it resets all disk
drive output lines to their
disabled state. Reset clears
the drive control register, sets
the data rate register to 250
kb/s, and sets the main status
register to 80. The mode
register default values are
given in the mode register
description. To prevent
glitches from activating the
reset sequence, attach a
1000 pF capacitor to this pin.
95, 94
MTR0,
MTR1
MTR1
O
Motors. These high drive
open drain outputs are motor
enable signals for drives 0
and 1. These pins contain
encoded drive select
information if bit 7 of the
configuration register is set.
Otherwise they are controlled
through bits in the drive
control register.
open drain outputs are motor
enable signals for drives 0
and 1. These pins contain
encoded drive select
information if bit 7 of the
configuration register is set.
Otherwise they are controlled
through bits in the drive
control register.
76
OSC1
I
Oscillator. One side of an
external 24 MHz crystal is
attached here. This pin is tied
low if an external clock is
used.
external 24 MHz crystal is
attached here. This pin is tied
low if an external clock is
used.
75
OSC2/CLK
I/O
Oscillator Clock. One side of
an external 24 MHz crystal is
attached here. If a crystal is
not used, a TTL or CMOS
compatible clock is connected
to this pin.
an external 24 MHz crystal is
attached here. If a crystal is
not used, a TTL or CMOS
compatible clock is connected
to this pin.
26
∼
19
PD0
∼
PD7
O
Port Data. These bidirectional
pins transfer data to and from
the peripheral data bus.
These pins have high current
drive capability.
pins transfer data to and from
the peripheral data bus.
These pins have high current
drive capability.
30
PE
I
Paper End. This input is set
high by the printer when it is
out of paper.
high by the printer when it is
out of paper.
38
POE
I
Port Output Enable. When
low, data written to the
parallel port data register is
output through PD0
low, data written to the
parallel port data register is
output through PD0
∼
PD7.
When high, PD0
∼
PD7 are in
a high impedance state and
act as inputs. This pin is
usually tied low for printer
operation.
act as inputs. This pin is
usually tied low for printer
operation.
83
PUMP/
PREN
PREN
I/O
Pump/Precompensation
Enable. When the PU bit is
set in mode command, this
pin is an output that indicates
when the charge pump is
making a correction.
Otherwise this pin is an input
that sets the precomp mode
(Table 11). If pin is configured
as PUMP, PREN is assumed
high.
Enable. When the PU bit is
set in mode command, this
pin is an output that indicates
when the charge pump is
making a correction.
Otherwise this pin is an input
that sets the precomp mode
(Table 11). If pin is configured
as PUMP, PREN is assumed
high.
Pin
Number
Pin Symbol
Pin
Type
Description
15
RD
I
Read. When this input is low
while the chip is selected, the
CPU can read status
information or data from the
selected register.
while the chip is selected, the
CPU can read status
information or data from the
selected register.
78
RDATA
I
Read Data. The active low
raw data read from the disk is
connected here.
raw data read from the disk is
connected here.
50, 49
RI1, RI2
I
Ring Indicator. When low,
this input indicates that a
telephone ringing signal has
been received by the modem
or data set. RI is a modem
status input whose condition
can be tested by the CPU
through reading bit 6 (RI) of
the MSR. Bit 6 is the
complement of RI. Bit 2
(TERI) of the MSR shows
whether RI has changed state
since the previous reading of
the MSR. Whenever the RI bit
of the MSR changes from a
high to a low state, an
interrupt is generated if the
modem status interrupt is
enabled.
this input indicates that a
telephone ringing signal has
been received by the modem
or data set. RI is a modem
status input whose condition
can be tested by the CPU
through reading bit 6 (RI) of
the MSR. Bit 6 is the
complement of RI. Bit 2
(TERI) of the MSR shows
whether RI has changed state
since the previous reading of
the MSR. Whenever the RI bit
of the MSR changes from a
high to a low state, an
interrupt is generated if the
modem status interrupt is
enabled.
88
RPM/LC
O
Revolution Per Minute/Low
Current. This high drive open
drain output pin has two
functions based on the
selection of the DRVTYP pin:
(1) When using a dual-speed
spindle motor flexible drive
(DRVTYP pin low), this output
is used to set the spindle
motor speed to either 300
RPM or 360 RPM. In this
mode, this output goes low
when 250/300 kb/s data rate
is chosen in the data rate
register, and high when 500
kb/s is chosen. (2) When
using a single-speed spindle
motor flexible drive (DRVTYP
pin high), this pin indicates
when to reduce the write
current to the drive. This
output is high for high density
media (when 500 kb/s is
chosen).
Current. This high drive open
drain output pin has two
functions based on the
selection of the DRVTYP pin:
(1) When using a dual-speed
spindle motor flexible drive
(DRVTYP pin low), this output
is used to set the spindle
motor speed to either 300
RPM or 360 RPM. In this
mode, this output goes low
when 250/300 kb/s data rate
is chosen in the data rate
register, and high when 500
kb/s is chosen. (2) When
using a single-speed spindle
motor flexible drive (DRVTYP
pin high), this pin indicates
when to reduce the write
current to the drive. This
output is high for high density
media (when 500 kb/s is
chosen).
55, 43
RTS1,
RTS2
RTS2
O
Request to Send. When low,
this output indicates to the
modem or data set that the
UART is ready to exchange
data. RTS can be set to an
active low by programming bit
1 (RTS) of the MCR. A
master reset operation sets
this signal to its inactive (high)
state. If XTSEL is high during
reset, loop mode operation
holds this signal in its inactive
state. If low, MCR bit 1
controls the associated pin
during loop mode operation.
this output indicates to the
modem or data set that the
UART is ready to exchange
data. RTS can be set to an
active low by programming bit
1 (RTS) of the MCR. A
master reset operation sets
this signal to its inactive (high)
state. If XTSEL is high during
reset, loop mode operation
holds this signal in its inactive
state. If low, MCR bit 1
controls the associated pin
during loop mode operation.
– 8 –
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