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3. PIN DESCRIPTION (M5105)
Pin
Number
Pin Symbol
Pin
Type
Description
11
∼
2
A0
∼
A9
I
I/O Address. Address signals
connected to these inputs
select the active register
during a CPU read or write.
See each individual sections
(UART, parallel port, FDC,
etc.) for details of each
registers.
connected to these inputs
select the active register
during a CPU read or write.
See each individual sections
(UART, parallel port, FDC,
etc.) for details of each
registers.
31
ACK
I
Acknowledge. When set low
by the printer, this input
indicates that the printer has
received data.
by the printer, this input
indicates that the printer has
received data.
12
AEN
I
Address Enable. When high,
this input disables function
selection via A0
this input disables function
selection via A0
∼
A9.
35
AFD
O
Automatic Feed. When low,
this tells the printer to
automatically line feed after
each line printed.
this tells the printer to
automatically line feed after
each line printed.
57, 41
BOUT1,
BOUT2
BOUT2
O
Baud Rate Output. This multi-
function pin gives the
associated serial channel
baudout signal, after data of
10h has been written to the
IIR (interrupt identification
register) and DLAB=1. It also
gives the composite serial
data output signal for the
associated channel after a
reset or after 00h is written to
IIR or DLAB=0.
function pin gives the
associated serial channel
baudout signal, after data of
10h has been written to the
IIR (interrupt identification
register) and DLAB=1. It also
gives the composite serial
data output signal for the
associated channel after a
reset or after 00h is written to
IIR or DLAB=0.
32
BUSY
I
Printer Busy. This input is
set high by the printer when
the printer can not accept
another character.
set high by the printer when
the printer can not accept
another character.
41, 43, 44,
54, 55,
16, 57
54, 55,
16, 57
CRB0
∼
4,
CRB6
∼
7
I/O
Configuration Register Bits.
These dual-function pins act
as inputs during reset (if
CRPE=0) to determine the
state of the configuration
register bits. The bits of the
configuration register is the
complement of these inputs.
A 10K resistor can be used to
pull these pins to the required
signal levels. These pins are
outputs when the chip is not
in reset. These pins have dual
functions, as follows:
SOUT2/CRB0, RTS2/CRB1,
DTR2/CRB2, DTR1/CRB3,
RTS1/CRB4, HCS0/CRB6,
SOUT1/CRB7.
These dual-function pins act
as inputs during reset (if
CRPE=0) to determine the
state of the configuration
register bits. The bits of the
configuration register is the
complement of these inputs.
A 10K resistor can be used to
pull these pins to the required
signal levels. These pins are
outputs when the chip is not
in reset. These pins have dual
functions, as follows:
SOUT2/CRB0, RTS2/CRB1,
DTR2/CRB2, DTR1/CRB3,
RTS1/CRB4, HCS0/CRB6,
SOUT1/CRB7.
Pin
Number
Pin Symbol
Pin
Type
Description
17
CRPE
I/O
Configuration Register
Program Enable. This multi-
function pin selects between
internal or external default
values for the configuration
register and whether the
configuration register can be
initialized through hardware
or software. The chip checks
this pin during reset, at that
time it acts as an input. If it is
low during reset, the
configuration register defaults
to the complement of the
CPB0
Program Enable. This multi-
function pin selects between
internal or external default
values for the configuration
register and whether the
configuration register can be
initialized through hardware
or software. The chip checks
this pin during reset, at that
time it acts as an input. If it is
low during reset, the
configuration register defaults
to the complement of the
CPB0
∼
4, 6, 7 pin states. If it
is high, it defaults to 00h. This
pin must always have a pull
up or pull down resistor (10K)
attached to pull it to the
required signal level. This pin
is driven by the chip when not
in reset. Regardless of the
initial polarity of this pin, the
configuration register can be
programmed whenever
master reset is inactive.
pin must always have a pull
up or pull down resistor (10K)
attached to pull it to the
required signal level. This pin
is driven by the chip when not
in reset. Regardless of the
initial polarity of this pin, the
configuration register can be
programmed whenever
master reset is inactive.
51, 48
CTS1,
CTS2
CTS2
I
Clear to Send. When low,
these inputs indicate that the
modem or data set is ready to
exchange data. CTS is a
modem status input whose
conditions can be tested by
the CPU via reading bit 4
(CTS) of the modem status
register (MSR). Bit 4 is the
complement of CTS. Bit 0
(DCTS) of the MSR shows
whether CTS has changed
state since the previous
reading of the MSR. CTS has
no effect on the transmitter.
Whenever the DCTS bit of the
MSR changes state, an
interrupt is generated if the
modem status interrupts is
enabled.
these inputs indicate that the
modem or data set is ready to
exchange data. CTS is a
modem status input whose
conditions can be tested by
the CPU via reading bit 4
(CTS) of the modem status
register (MSR). Bit 4 is the
complement of CTS. Bit 0
(DCTS) of the MSR shows
whether CTS has changed
state since the previous
reading of the MSR. CTS has
no effect on the transmitter.
Whenever the DCTS bit of the
MSR changes state, an
interrupt is generated if the
modem status interrupts is
enabled.
60
∼
64,
66
∼
68
D0
∼
D7
I/O
Data Bus. This bus contains
eight tri-state input/output
lines. The bus provides
bidirectional communications
between the M5105 chip and
the CPU. Data, control words,
and status information are
transferred via the data bus.
eight tri-state input/output
lines. The bus provides
bidirectional communications
between the M5105 chip and
the CPU. Data, control words,
and status information are
transferred via the data bus.
70
DAK
I
DMA Acknowledge. This is
an active low input used to
acknowledge DMA requests
and to enable the RD and WR
inputs. This signal is enabled
when D3 of the drive control
register is set. The SPECIFY
command must be used to
enable the DMA mode.
an active low input used to
acknowledge DMA requests
and to enable the RD and WR
inputs. This signal is enabled
when D3 of the drive control
register is set. The SPECIFY
command must be used to
enable the DMA mode.
– 5 –
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