Read Sony CDP-LSA1 / MDS-LSA1 / STR-LSA1 Service Manual online
16
(6) PLL circuit (LINK)
The MDS-LSA1 and STR-LSA1 receives, records or plays sounds from other devices. Consequently, the clocks must be generated
according to the sampling frequency (fs) of the audio signals received. The signal is therefore synchronized by the PLL circuit mounted
externally to LINK.
externally to LINK.
SYTO terminal (Pin 26) ........... When the i.LINK signal is received, the 1/8 fs clock of the signal received is output.
When fs is 44.1 kHz: 5.51 kHz.
PLLCKI terminal (Pin 27) ........ The 256 fs clock generated in the external PLL circuit is input.
When fs is 44.1 kHz: 11.289 MHz.
1/8OUT terminal (Pin 25) ........ The 1/2048 signal of the signal input to the PLLCKI terminal (Pin 27) is output.
When fs is 44.1 kHz: 5.51 kHz.
(Repair Tips) When i.LINK audio signal cannot be received
When i.LINK audio signal cannot be received, check the SYTO terminal of LINK (Pin 26). If the presence of a clock which is 1/8 times
the sampling frequency can be confirmed at the SYTO terminal, it means that the i.LINK circuit is performing reception operations normally,
and the error is due to malfunction of the digital audio processing circuit after the i.LINK circuit. If the clock cannot be confirmed at the
SYTO terminal, check the signal path between PHY and LINK and the PLL circuit.
and the error is due to malfunction of the digital audio processing circuit after the i.LINK circuit. If the clock cannot be confirmed at the
SYTO terminal, check the signal path between PHY and LINK and the PLL circuit.
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