CDP-LSA1, MDS-LSA1, STR-LSA1 - Sony Audio Service Manual (repair manual)

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Section

Title

Page

1. Name .......................................................................................................................................................................................................... 3
2. Circuit Configuration .................................................................................................................................................................................. 3

(1) PHYSICAL LAYER (PHY) ............................................................................................................................................................... 3
(2) LINK LAYER (LINK) ....................................................................................................................................................................... 4
(3) Application Layer ............................................................................................................................................................................... 4

3. System Configuration ................................................................................................................................................................................. 5

(1) ROOT .................................................................................................................................................................................................. 5
(2) Cycle Signal ........................................................................................................................................................................................ 5
(3) Transmission and Reception of Data .................................................................................................................................................. 6
(4) Data Transmission Speed ................................................................................................................................................................... 6
(5) Data Type ............................................................................................................................................................................................ 7

4. System Operations ...................................................................................................................................................................................... 8

(1) Signal Terminal ................................................................................................................................................................................... 8
(2) Cable Bias Voltage .............................................................................................................................................................................. 8
(3) Bus Reset ............................................................................................................................................................................................ 9
(4) LINC ................................................................................................................................................................................................. 10
(5) i.LINK Signals .................................................................................................................................................................................. 11

1. Power Supply Circuit ............................................................................................................................................................................... 13

(1) Starting PHY and LINK ................................................................................................................................................................... 13
(2) Output of Cable Bias Voltage (PHY) ................................................................................................................................................ 13

2. Clock Circuit ............................................................................................................................................................................................ 13

(1) Master Clock (PHY, LINK) .............................................................................................................................................................. 13
(2) Cycle Signal (PHY) .......................................................................................................................................................................... 13

3. Signal Circuit ............................................................................................................................................................................................ 13

(1) i.LINK Signal Input (PHY) .............................................................................................................................................................. 13
(2) Communication of PHY and LINK .................................................................................................................................................. 13
(3) Packet Data (LINK) .......................................................................................................................................................................... 14
(4) Communication Between LINK and Microprocessor ...................................................................................................................... 14
(5) Communication with Playback Circuit (LINK) ............................................................................................................................... 15
(6) PLL Circuit (LINK) .......................................................................................................................................................................... 16

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The IEEE1394, a high speed communication digital interface developed in the PC industry as standard, was standardized by the IEEE

(Institute of Electrical and Electronics Engineers). To give this high speed digital serial interface a name which is more familiar than IEEE1394,
Sony proposed the name “i.LINK”.
i.LINK is a name of the IEEE1394-1995 and the expansion specifications. It is called “Fire Wire” by Apple Computer in the U.S.

The configuration of the i.LINK circuit can be divided into three layers: PHYSICAL LAYER, LINK LAYER, APPLICATION and

TRANSACTION LAYER.

With the IEEE1394, the contents of the PHYSICAL LAYER, LINK LAYER, and TRANSACTION LAYER are defined. The APPLICA-

TION above is defined by the IEC61883 standard for AV equipment, and OHCI (PCI-1394bridge) for PCs, etc.

In the CDP/MDS/STR-LSA1 circuit, the operations are controlled by the three ICs-PHY, LINK, and SYSTEM CONTROL.

The i.LINK signals sent between units are H or L digital signals. The PHYSICAL LAYER plays the role of correctly sending this

electrical signal output. It is sometimes refereed to as PHY. In the LISSA series i.LINK circuit, operations are controlled by one IC (CXD1945R).

PHY recognizes the input electrical signal as digital signal, and outputs to the LINK LAYER.

It also sends the i.LINK signal (packet data) input to the next device.

If PHY is started, it functions as a repeater which sends the i.LINK signal to other devices. Therefore, there are models which supply

power to the PHY even when the power of the unit is OFF so that the function for passing the i.LINK signal is not suspended.

PHY also detects bus resets generated when a new device is connected or disconnected.

Some PCs and portable equipment may not supply power to the PHY. Take note that this may not be indicated in instruction manuals.

APPLICATION &

TRANSACTION LAYER

LINK LAYER

IEC61883/OHCI

IEEE1394

PHYSICAL LAYER

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Electric signals detected by the PHY are decoded in the logic layer to detect the contents of the signal. This detecting layer is the logic

layer. The logic layer is called LINK. In LISSA series i.LINK circuit, one IC (CXD3202AR) controls operations. It also has a PLL circuit to
read received audio signals.

In LINK, i.LINK signals are decided to verify the destination sent to and type. If the destination is another device, the contents will be

ignored. If the destination is itself or all devices, the type of signal will be verified. If the type can be read by itself, the i.LINK signal is output
to the application layer. If the type cannot be read, the application layer is notified that it cannot be read.

If the unit is the ROOT which is the master of the system, the i.LINK sync signal is controlled by LINK. Consequently, power is supplied

to LINK like PHY even when the power is OFF.

The i.LINK signal output from LINK is received as a command. The layer performing the main operations of the unit is the application

layer. The microprocessor controls the operations in the i.LINK circuit of the LISSA series.

SYSTEM CONTROL

LINK

CDP-LSA1

MDS-LSA1

STR-LSA1

PHY

SYSTEM CONTROL

LINK

PHY

SYSTEM CONTROL

LINK

PHY