Read Sony CDP-LSA1 / MDS-LSA1 / STR-LSA1 Service Manual online
13
II
. CIRCUIT OPERATIONS
1. POWER SUPPLY CIRCUIT
(1) Starting PHY and LINK
3.3 V drive voltage (3.5 V for MDS-LSA1 only) is supplied to PHY and LINK from the power supply circuit. PHY starts up when voltage
is supplied to the LPS terminal (Pin 5), while LINK starts when reset is cleared by the H input to the RESET terminal (Pin 85).
(2) Output of cable bias voltage (PHY)
When PHY starts, cable bias voltage (1.85 V) is output from the TBIAS2/TBIAS0 terminal (Pins 46/48). The cable bias voltage is output
to TA2N /TA2P/TA0N/TA0P terminals via the buffer (transistor). When the AC power is turned ON/OFF, the transistor goes OFF by the
signal output from the microprocessor, and cable bias is muted to prevent PHY mis-operations.
signal output from the microprocessor, and cable bias is muted to prevent PHY mis-operations.
2. CLOCK CIRCUIT
(1) Master clock (PHY, LINK)
The master clock of the i.LINK operation circuit is the 24.576 MHz of the crystal oscillator connector to the XO/XI terminal of PHY (Pin
32/33). This clock is divided by 1/2 by PHY, and output to the SYSCLK terminal (Pin 83) of LINK from the SCLK terminal (Pin 8) of PHY.
If PHY and LINK are not started, check the master clock input.
(2) Cycle signal (PHY)
When an external device is connected, and the cable bias voltage is output from the external device to the i.LINK terminal, it is detected
by the TA2N/TA2P/TA0N/TA0P terminals (Pins 51/52/59/60) of PHY, and PHY performs bus reset operations. When an external device is
detected, and the ROOT device is determined by the i.LINK system, the cycle signal (8 kHz/125 µs) which is the sync signal of i.LINK will
be output from ROOT.
detected, and the ROOT device is determined by the i.LINK system, the cycle signal (8 kHz/125 µs) which is the sync signal of i.LINK will
be output from ROOT.
When the unit is the ROOT, the cycle signal is generated inside PHY, and output from the TA2N/TA2P/TA0N/TA0P terminals (Pins 51/
52/59/60).
(Note) When no cycle signal is output
When other devices are not detected, the cycle signal will not be output. Consequently, it will not be output if other devices are not
connected to the unit or when a VAIO PC which has not been turned ON is connected.
3. SIGNAL CIRCUIT
(1) i.LINK signal input (PHY)
The i.LINK signal input from other devices are input as the TB2N and TB2P signals of the i.LINK terminal, or the differential signal of
the TB0N and TB0P. These signals become inversed waveforms.
(2) Communication of PHY and LINK
Packet data is extracted from the input i.LINK signal inside the PHY, and output from the DATA0 to 3 terminals (Pins 13/14/16/17) to
LINK. At this time, the control signal of mutual communication is output or input from or to the CTL0/CTL1 terminal (Pin 10/11) of PHY.
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