TU-X1E (serv.man8). Major IC Informations - Sharp TV Service Manual (repair manual). Page 14

TU-X1E/RU

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45,46

CK, CK

I

Clock: CK and CK# are differential clock inputs. 
All adress and control input signals are sampled on the positive edge of CK and nega-
tive edge of CK#. 
Output (read) data is referenced to the both edges of CK. Internal clock signals are 
derived from CK/CK#

44

CKE

I

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, 
and device input buffers and output drivers. 
Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all 
banks idle), or Active Power-Down (row Active in any bank). 
CKE is synchronous for power down entry and exit, and for self refresh entry. 
CKE is asynchronous for self refresh exit, and and for output disable. 
CKE must be maintained high throughout Read and Write accesses. 
Input buffers, excluding CK, CK# and CKE are disabled during Power-Down. 
Input buffers, excluding CKE, are disabled during Self Refresh.

24

CS

I

Chip Select: CS# enables (resistered LOW) and disables (resistered HIGH) the com-
mand decoder. 
All commands are masked when CS# is resisters HIGH. 
CS# provides for external bank selection on system with multiple banks. 
CS# is considered part of the command code.

23,22,21

RAS, CAS, WE

I

Command Inputs: RAS, CAS and WE (along with CS) define the command being 
entered.

20, 49

LDM,UDM

I

Input Data Mask: DM is an input mask signal for write data. 
Input data is masked when DM is sampled HIGH along with that input data during a 
WRITE access. 
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.

26, 27

BA0 - BA1

I

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE 
or PRECHARGE command is being applied. 

28, 29, 30, 31, 
32, 35, 36, 37, 

38, 39, 40, 41, 42

A [0:12]

I

Address Inputs: Provided the row address for ACTIVE commands, and the column 
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one 
location out of the memory array in the respective bank. 
A10 is sampled during a PRECHARGE command to determine whether the PRE-
CHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). 
If only one bank is to be precharged, the bank is selected by BA0, BA1. 
The address inputs also provide the op-code during MODE REGISTER SET com-
mands.
BA0 and BA1 define which mode register is loaded during the MODE RESISTER SET 
command (MRS or EMRS).

2, 4, 5, 7, 8, 10, 

11, 13, 54, 56, 57, 

59, 60, 62, 63, 65

DQ

I/O

Data Input/ Output:  Data bus.

16,

51

LDQS,

UDQS,

I/O

Data Strobe: output with read data, input with write data. Edge-aligned with read data, 
centered in write data. Used to capture write data. 
For the *16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the 
data on DQ8-DQ15. 
LDQS is NC on *4 and *8.

14, 17, 19, 25, 

43, 50, 53

NC

 -

No Connect: No internal electrical connection is present.

3, 9, 15, 55, 61

VDDQ

 -

DQ Power Supply: 2.5V 

± 0.2V.

6, 12, 52, 58, 64

VSSQ

 -

DQ Ground.

1, 18, 33

VDD

 -

Power Supply: 2.5V 

± 0.2V.

34,48,66

VSS

 -

Ground.

49

VREF

 -

SSTL_2 reference voltage.