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TU-X1E/RU
7 – 10
6. RH-IXC505WJQZQ 512Mbit DDR2 SDRAM
Pin No.
Pin Name
I/O
Pin Function
53, 52
CK, CK
I
Clock: CK and CK# are differential clock inputs.
All address and control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#.
Output (read) data is referenced to the crossings of CK and CK# (both directions of
crossing).
All address and control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#.
Output (read) data is referenced to the crossings of CK and CK# (both directions of
crossing).
41
CKE
I
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals
and device input buffers and output drivers.
Taking CKE Low provides Precharge Power-Down and Self Refresh operation(all
banks idle), or Active Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry.
CKE is asynchronous for self refresh exit.
CKE must be maintained high throughout read and write accesses.
Input buffers, excluding CK, CK#, ODT and CKE are disabled during powerdown.
Input buffers, excluding CKE, are disabled during self refresh.
and device input buffers and output drivers.
Taking CKE Low provides Precharge Power-Down and Self Refresh operation(all
banks idle), or Active Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry.
CKE is asynchronous for self refresh exit.
CKE must be maintained high throughout read and write accesses.
Input buffers, excluding CK, CK#, ODT and CKE are disabled during powerdown.
Input buffers, excluding CKE, are disabled during self refresh.
51
CS
I
Chip Select: All commands are masked when CS# is registered HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is considered part of
the command code.
for external bank selection on systems with multiple banks. CS# is considered part of
the command code.
19
ODT
I
On Die Termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS#,
RDQS, RDQS#, and DM signal for x4/x8 configurations. For x16 configuration, ODT is
applied to each DQ, UDQS/UDQS#, LDQS/LDQS#, UDM, and LDM signal. The ODT
pin will be ignored if the Extended Mode Register Set(EMRS) is programmed to dis-
able ODT.
the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS#,
RDQS, RDQS#, and DM signal for x4/x8 configurations. For x16 configuration, ODT is
applied to each DQ, UDQS/UDQS#, LDQS/LDQS#, UDM, and LDM signal. The ODT
pin will be ignored if the Extended Mode Register Set(EMRS) is programmed to dis-
able ODT.
77, 76, 70
RAS, CAS, WE
I
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
entered.
62, 66
UDM
LDM
I
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write access.
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
For x8 device, the function of DM or RDQS/RDQS# is enabled by EMRS command.
DM is sampled HIGH coincident with that input data during a Write access.
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
For x8 device, the function of DM or RDQS/RDQS# is enabled by EMRS command.
42, 71
BA0 - BA1
I
Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write
or Precharge command is being applied.
Bank address also determines if the mode register or extended mode register is to be
accessed during a MRS or EMRS cycle.
or Precharge command is being applied.
Bank address also determines if the mode register or extended mode register is to be
accessed during a MRS or EMRS cycle.
13,
43-50,
72-75
A0 - A12
I
Address Inputs: Provided the row address for Active commands and the column
address and Auto Precharge bit for Read/Write commands to select one location out
of the memory array in the respective bank.
A10 is sampled during a Precharge command to determine whether the Precharge
applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2. The
address inputs also provide the opcode during Mode Register Set commands.
address and Auto Precharge bit for Read/Write commands to select one location out
of the memory array in the respective bank.
A10 is sampled during a Precharge command to determine whether the Precharge
applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2. The
address inputs also provide the opcode during Mode Register Set commands.
2, 4, 6, 8, 21, 23,
25, 27, 34, 38,
55, 59, 64, 68,
55, 59, 64, 68,
79, 83
DQ [0:15]
I/O
Data Input/ Output: Bi-directional data bus.
29,
61,
57,
61,
57,
81
UDQS#
UDQS,
LDQS#,
LDQS
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data,
centered in write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the
data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the
EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS
may be used in single ended mode or paired with optional complementary signals
DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system dur-
ing both reads and writes. A control bit at EMRS(1)[A10] enables or disables all com-
plementary data strobe signals.
centered in write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the
data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the
EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS
may be used in single ended mode or paired with optional complementary signals
DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system dur-
ing both reads and writes. A control bit at EMRS(1)[A10] enables or disables all com-
plementary data strobe signals.
10, 12, 14, 15,
16, 32, 36,
NC
-
No Connect: No internal electrical connection is present.
1, 3, 5, 7, 12, 18,
20, 22, 24, 26,
28, 63, 67, 80, 84
VDD/VDDQ
-
Power Supply/DQ Power Supply: 1.8V
± 0.1V.
11, 17, 30, 31,
33, 35, 37, 39,
54, 56, 58, 60,
54, 56, 58, 60,
65, 69, 82
VSS/VSSQ
-
Ground/DQ Ground.
9
VDDL
-
DLL Power Supply: 1.8V
± 0.1V.
78
VSSL
-
DLL Ground.
40
VREF
-
Reference voltage.
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