TU-X1E (serv.man8). Major IC Informations - Sharp TV Service Manual (repair manual). Page 9

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5. VHISII9134-1Q  HDMI Transmitter
Pin No.
Pin Name
I/O
Pin Function
Digital Video Input Pins.
98,97,96,95,94,9
3,92,91,90,86,85,
84,
D[0:11]
I
These are the lower 12bits of the 36-bit pixel bus.
These pins are highly configrable, and support multiple RGB and YCbCr format.
83,82,81,80,79,7
8,77,75,74,73,72,
71,
D[12:23]
I
These are the middle 12 bits of the 36-bit pixel bus. 
70,69,68,67,63,6
2,61,60,59,58,57,
56
D[24:35]
I
These are the upper 12 bits of the 36-bit pixel bus.
88
IDCK
I
Input Data Clock.
1
DE
I
Data enable.
2
HSYNC
I
Horizontal Sync Input control signal.
3
VSYNC
I
Vertical Sync Input control signal.
Digital Audio Output Pins.
11
SCK
I
I2S Serial Clock Input.
10
WS
I
I2S Word Select Input.
9
SD0
I
I2S Serial Data Input. 0
8
SD1
I
I2S Serial Data Input. 1
7
SD2
I
I2S Serial Data Input. 2
6
SD3
I
I2S Serial Data Input. 3
23,21,19,17
DL[3:0]
I
One-bit Audio Data Left [3:0]
22,20,18,16
DR[3:0}
I
One-bit Audio Data Right [3:0]
15
DCLK
I
One-bit Audio Clock Input.
5
MCLK
I
Audio Input Master Clock.
4
SPDIF
I
S/PDIF Audio Input. 
Configuration/Programming Pins.
51
HPD
I
Hot Plug Detect Input
52
RSVDL
I
Reserved for use by Sillicon Image and must be tied LOW.
24
INT
O
Interrupt Output.
Control Pins.
50
CI2CA
I
I2C Device Adress Select. 5V Tolerant.
25
RESET#
I
Reset Pin. Active LOW.  5V Tolerant.
48
CSCL
I
Configuration/Status I2C Clock. 
49
CSDA
I/O
Configuration/Status I2C Data. (Open drain output) 
46
DSCL
I
DDC I2C Clock . (Open drain output) 
47
DSDA
I/O
DDC I2C Data .  (Open drain output) 
Differential Signal Data Pins.
34
TX0+
O
TMDS output data pair.  
33
TX0-
O
37
TX1+
O
TMDS output data pair. 
36
TX1-
O
40
TX2+
O
TMDS output data pair. 
39
TX2-
O
31
TXC+
O
TMDS output clock pair. 
30
TXC-
O
27
EXT_SWING
I
Voltage swing adjust. A resister is tied from this pin to AVCC. This rester determines 
the amplitude of the voltage swing. Recommend 698
Ω 1% when source termination 
and leakage bias is on and 845
Ω 1% when source termination and leakage bias is off.
Power and Ground Pins.
12,55,64,76,99
CVCC18
---
Digital Logic core VCC. 1.8V
14,53,66,89
IOVCC33
---
Input/Output pin VCC .  3.3V
44
AVCC33
---
Analog VCC. 3.3V
32,38
AVCC18
---
Analog VCC.  1.8V.
26,29,35,41,43
AGND
---
Analog ground.
28
PVCC1
---
TMDS core PLL power. 1.8V
42
PVCC2
---
Filter PLL power. 1.8V
45
DDCPWR5V
---
Power reference signal.  Used to supply power to the DDC I2C pads when chip is 
powered off. 5V
13,54,65,87,100
GND
---
Digital ground..
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