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TU-X1E/RU
7 – 17
2. VHIAK4384ET-1Y 24bit-DAC
71
CYOUT2
/YOUT2
/VOUT2
/YOUT2
/VOUT2
O
It is color difference CY signal output or brightness output or composite output terminal2.
73
PROUT1
O
Color difference Pr signal output terminal 1
It is possible to switch in the D5 mode and the D4 mode.
It is possible to switch in the D5 mode and the D4 mode.
74
PBOUT1
/COUT1
/COUT1
O
Color difference Pb signal output terminal 1
It is possible to switch in the D5 mode and the D4 mode.
It is possible to switch in the D5 mode and the D4 mode.
75
CYOUT1
/YOUT1
/VOUT1
/YOUT1
/VOUT1
O
It is color difference CY signal output or brightness output or composite output terminal1.
77
78
79
78
79
SW3
SW2
SW1
SW2
SW1
I
D Terminal discrimination connection detection signal input
The discrimination result is output to status register.
The discrimination result is output to status register.
81
87
93
87
93
DL1_1
DL1_2
DL1_3
DL1_2
DL1_3
I
D Terminal discrimination number of scanning lines information signal input
The discrimination result is output to status register.
The discrimination result is output to status register.
82
88
94
88
94
CY1
CY2
CY3
CY2
CY3
I
Component Y signal input
83
89
95
89
95
DL2_1
DL2_2
DL2_3
DL2_2
DL2_3
I
D Terminal discrimination I/P information signal input
The discrimination result is output to status register.
The discrimination result is output to status register.
84
90
96
90
96
PB1
PB1
PB1
PB1
PB1
I
Color-difference signal PB input
RGB signal can also be inputted.
RGB signal can also be inputted.
85
91
97
91
97
DL3_1
DL3_2
DL3_3
DL3_2
DL3_3
I
D Terminal discrimination aspect ratio information signal input
The discrimination result is output to status register.
The discrimination result is output to status register.
86
92
98
92
98
PR1
PR2
PR3
PR2
PR3
I
Color-difference signal PR input
RGB signal can also be inputted.
RGB signal can also be inputted.
Pin No.
Pin Name
I/O
Pin Function
1
MCLK
I
Master Clock input pin.
An external TTL clock should be input on this pin.
An external TTL clock should be input on this pin.
2
BICK
I
Audio serial data clock pin.
3
SDTI
I
Audio serial data input pin.
4
LRCK
I
L/R clock pin.
5
PDN
I
Power-Down mode pin.
When at "L", the AK4384 is in the power-down mode and is held in reset.
The AK4384 should always be reset upon power-up.
When at "L", the AK4384 is in the power-down mode and is held in reset.
The AK4384 should always be reset upon power-up.
6
SMUTE CSN
I
Soft mute pin in parallel mode
"H": Enable, "L" : Disable
Chip select pin in serial mode.
"H": Enable, "L" : Disable
Chip select pin in serial mode.
7
ACKS CCLK
I
Auto setting mode pin in parallel mode.
"L": manual setting mode. "H": auto setting mode.
Control data clock pin in serial mode.
"L": manual setting mode. "H": auto setting mode.
Control data clock pin in serial mode.
8
DID0 CDTI
I
Audio data interface format pin in parallel mode.
Control data input pin in serial mode.
Control data input pin in serial mode.
9
P/S
I
Parallel/Serial select pin.
"L": serial control mode.. "H": Parallel control mode.
"L": serial control mode.. "H": Parallel control mode.
10
AOUTR
O
Rch analog output pin.
11
AOUTL
O
Lch analog output pin.
12
VCOM
O
Common voltage pin, VDD/2
Nominally connected to VSS with a 0.1
Nominally connected to VSS with a 0.1
µF ceramic capacitor in parallel with a 10µF electrolytic cap.
13
VSS
-
Ground pin.
14
VDD
-
Power supply pin.
15
DZFR
O
Rch data zero input detect pin.
16
DZFL
O
Lch data zero input detect pin.
Pin No.
Pin Name
I/O
Pin Function
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