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LC-46X8E/S/RU
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1.4. IC3301 (RH-iXC010WJQZQ)
1.4.1 Block Diagram
1.4.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
Destination
Ball Assignments for CPU Host Interface.
K20, K19, K18,
K17, L20, L19,
L18, L17
K20, K19, K18,
K17, L20, L19,
L18, L17
A_D[7:0]
I/O
Multiplexed address and data bus powered by VDDH/VSS. ADAT_O-7
CPU
M17, M18, M19,
M20, N20, N19,
N18, N17
M20, N20, N19,
N18, N17
ADDR[7:0]
I
CPU Address. (not connected)
TP3301-8
CPU
J18
ALE
I
Address latch enables.
8051_ALE
CPU
J19
WR#
I
CPU Write.
8051_WR
CPU
J20
RD#
I
CPU Read.
8051_RD
CPU
H17
SDA
I/O
I2C data.
R-+3.3V
H18
SCL
I
I2C clock.
R-+3.3V
J17
CPU_CS
I
UX chip select pin from MCU. Active Low.
8051_CS
CPU
Ball Assignments for Analog Support Interface.
W1
W1
XTALI
I
Input for Clock Synthesizer. Supports 24MHz Oscillator or
crystal powered by analog PLL.
crystal powered by analog PLL.
XTAL
X-TAL,27M
Y1
XTALO
O
Used in conjunction with XTALI for 24MHz crystal output
powered by analog PLL.
powered by analog PLL.
XTAL
X-TAL,27M
U2
MLF1
I
Low pass filter node for memory clock PLL powered by
analog PLL.
analog PLL.
CR_+B
R4
PLF2
I
Low pass filter node for video clock PLL powered by analog
PLL.
PLL.
+3.3V
Ball Assignments for Analog Input Interface.
Y4
Y4
CVBS1
I
Composite video input 1.
MAIN_Y/V_TR
FROM-V-SW
V6
Y_G1
I
Y input 1 of component or G input 1 of PC RGB.
SCART_G_TR
FROM-V-SW
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