Read Sharp LC-46X8E Service Manual online
LC-46X8E/S/RU
5 – 6
W6
Y_G2
I
Y input 2 of component or G input 2 of PC RGB.
COMP_Y_TR
FROM-V-SW
Y6
Y_G3
I
Y input 3 of component or G input 3 of PC RGB.
DTM_Y
open
W2
CVBS_OUT1
I
CVBS Output 1. (not connected)
open
V2
CVBS_OUT2
I
CVBS Output 2. (not connected)
open
V9
C
I
C input of S-Video.
MAIN_C_TR
FROM-V-SW
W9
PB_B1
I
PB input 1 of component.
SCART_B_TR
FROM-V-SW
Y9
PB_B2
I
PB input 2 of component.
COMP_Pb_TR
FROM-V-SW
Y10
PB_B3
I
PB input 3 of component.
DTM_Pb
open
Y8
PR_R1
I
PR input 1 of component.
SCART_R_TR
FROM-V-SW
W8
PR_R2
I
PR input 2 of component.
COMP_Pr_TR
FROM-V-SW
V8
PR_R3
I
PR input 3 of component.
DTM_PR
open
W4, V4
FS2, FS1
I
SCART function select 2, 1.
W4
R-GND
U4, Y5
FB2, FB1
I
SCART FB input for Port 2, Port 1.
V4
R-GND
V10
AIN_H
I
Hsync input (PC RGB input)
PC-H
FROM EXT7
U10
AIN_V
I
Vsync input (PC RGB input)
PC-V
FROM EXT7
U8
PC_R
I
PC Red input.
PC_R
FROM EXT7
Y7
PC_G
I
PC Green input.
PC_G
FROM EXT7
W10
PC_B
I
PC Blue INPUT.
PC_B
FROM EXT7
Ball Assignments for Capture Interface (TV & RGB).
U18, U19, U20,
T20, T18, T17,
R19, R20
U18, U19, U20,
T20, T18, T17,
R19, R20
DPB[15:8]
(DP_B[15:8])
(DP_B[15:8])
I/O
Digital input port[15:8] (Output reserved)
AD_RA0-8
AD_GA0-8
AD_BA0-8
AD_GA0-8
AD_BA0-8
TO CPU
Y12, U13, V13,
W13, Y13, Y14,
W14, V14, U14,
U15, V15, W15,
Y16, W16, V16,
U16, U17, V17,
W17, Y17, Y18,
W18, V18, W19
W13, Y13, Y14,
W14, V14, U14,
U15, V15, W15,
Y16, W16, V16,
U16, U17, V17,
W17, Y17, Y18,
W18, V18, W19
DPA[23:0]
(DP_A[23:0])
(DP_A[23:0])
I/O
Digital input/output port [23:0]
AD_RA0-8
AD_GA0-8
AD_BA0-8
AD_GA0-8
AD_BA0-8
TO CPU
T19
DPB_CLK (CLK_B)
I/O
Digital port B CLK input/output. (no connected)
open
Y15
DPA_CLK (CLK_A)
I/O
Digital port A CLK input/output.
AD_CLK
TO CPU
W20
DPE_DE (DE_B)
I/O
DE input/output of Digital port B.
AD_DE
TO CPU
Y20
DPA_VS (VS_A)
I/O
Vsync input/output of Digital port A.
AD_VD
TO CPU
Y19
DPA_HS (HS_A)
I/O
Hsync input/output of Digital port A.
AD_HD
TO CPU
V20
DPB_VS (VS_B)
I/O
Vsync input/output of Digital port B. (no connected)
open
V19
DPB_HS (HS_B)
I/O
Hsync input/output of Digital port B. (no connected)
open
P19
HS
I/O
Hsync output for Digital port.
R-+B
P17
VS
I/O
Vsync output for Digital port.
R-+B
Ball Assignments for Frame Buffer Memory.
D3, C3, C2, C1,
A1, A2, A3, C5,
A4, B5, A5, D6,
A7, B7, C7, D7,
D8, C8, B8, A8,
D9, D10, C10,
B10, A10, A11,
B11, C11, D12,
A13, B13, C13
D3, C3, C2, C1,
A1, A2, A3, C5,
A4, B5, A5, D6,
A7, B7, C7, D7,
D8, C8, B8, A8,
D9, D10, C10,
B10, A10, A11,
B11, C11, D12,
A13, B13, C13
MD[31:0]
I/O
Memory data.
WX_MD31-0
TO SDRAM
F1, F2, F3, F4,
G4, G3, G2, G1,
H1, H2, H3, H4
G4, G3, G2, G1,
H1, H2, H3, H4
MA[11-0]
I/O
Memory Address.
WX_MA11-0
TO SDRAM
J2
RAS#
O
RAS# signal powered by VDDH/VSS.
WX_RAS
TO SDRAM
J1
CAS#
O
CAS# signal powered by VDDH/VSS.
WX_CAS
TO SDRAM
K1
WE#
O
WE#, write enable signal powered by VDDH/VSS.
WX_WE
TO SDRAM
J3
CS1#
O
Chip select 0 for the first 2/4 Mbyte of SGRAM/SDRAM
powered by VDDH/VSS.
powered by VDDH/VSS.
WX_CS1
TO SDRAM
J4
CS0#
O
Chip select 1 for the second 2/4 Mbyte of SGRAM/SDRAM
powered by VDDH/VSS.
powered by VDDH/VSS.
WX_CS0
TO SDRAM
D1
MCK0
O
Memory clock+.
WX_MCLK0
TO SDRAM
E1
MCK0#
O
Memory clock-.
WX_MCLK0#
TO SDRAM
B1, A6, A9, A12
DQM[3:0]
O
Read/Write bytes enable powered by VDDH/VSS.
WX_DQM3-0
TO SDRAM
K2
CLKE
O
Memory Clock Enable.
WX_CLKE
TO SDRAM
B2, B6, B9, B12
DQS[3:0]
I/O
Memory data strobe.
WX_DQS3-0
TO SDRAM
E3
MVREF
—
DDR voltage reference.
WX_DDR_VREF
TO SDRAM
K3
BA0
O
Bank address select.
WX_BA0
TO SDRAM
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
Destination
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