Read Sharp LC-46X8E Service Manual online
LC-46X8E/S/RU
5 – 7
K4
BA1
O
Bank address select.
WX_BA1
TO SDRAM
Ball Assignments for Power and Ground.
C14, C15, D13,
D14, D15, E13,
E14, E15, G16,
H5, H16, J5,
J16, K5, K16,
R16, T14, T15
C14, C15, D13,
D14, D15, E13,
E14, E15, G16,
H5, H16, J5,
J16, K5, K16,
R16, T14, T15
VDDC
—
1.2V Digital core power.
D1.2V
E4, E7
VSSR
—
Digital memory reference Ground.
GND
E2, E8
VDDR
—
2.5V Digital power for Memory.
2.5V
B4, C4, D4, D5,
D11, E5, E6, E9,
E10, E11, E12,
F5, G5
D11, E5, E6, E9,
E10, E11, E12,
F5, G5
VDDM
—
2.5V Memory interface power. Output driver.
2.5V
L16, M16, N16,
P16, T12, T13,
R17, R18
P16, T12, T13,
R17, R18
VDDH
—
3.3V Digital I/O power.
D3.3V
B3, C6, C9,
C12, D2, H8,
H9, H10, H11,
H12, H13, J8,
J9, J10, J11,
J12, J13, K8,
K9, K10,
K11,K12, K13,
L5, L8, L9, L10,
L11, L12, L13,
M8, M9, M10,
M11, M12, M13,
N8, N9, N10,
N11, N12, N13,
P18, T16, H20
C12, D2, H8,
H9, H10, H11,
H12, H13, J8,
J9, J10, J11,
J12, J13, K8,
K9, K10,
K11,K12, K13,
L5, L8, L9, L10,
L11, L12, L13,
M8, M9, M10,
M11, M12, M13,
N8, N9, N10,
N11, N12, N13,
P18, T16, H20
VSS
—
Core and Digital IO ground.
GND
W3
AVSS_BG_ASS
—
ADC ground.
GND
V3
AVDD3_BG_ASS
—
3.3V ADC power.
R-D3.3V
T3
PAVDD1
—
3.3V power for MCLK PLL.
R-D3.3V
T2
PAVSS1
—
Ground for MCLK PLL.
GND
R3
PAVSS2
—
Ground for PCLK PLL.
GND
T4
PAVDD2
—
3.3V power for PCLK PLL.
R-D3.3V
U6, T8, U7, U5
AVDD_ADC[4, 3, 2, 1]
—
1.2V power for analog ADC.
L-D1.2V
T6, T9, T7, T5
AVSS_ADC[4, 3, 2, 1]
—
Ground for analog ADC.
GND
U9, Y3
AVDD3_ADC[2, 1]
—
3.3V ADC power.
L-D3.3V
U3
AVDD3_OUTBUF
—
3.3V power for output buffer.
R-D3.3V
Y2
AVSS_OUTBUF
—
3.3V ground for output buffer.
GND
C18, C19
LVDS_VSSO
—
LVDS out buffer ground.
GND
C16
LVDS_VSSD
—
LVDS Digital ground.
GND
E16
LVDS_VSSA
—
LVDS analog ground.
GND
E18
LVDS_VSSP
—
LVDS PLL GND.
GND
D18
LVDS_VDDP
—
LVDS PLL VDD.
R-D1.2V
E17
LVDS_VDDA
—
LVDS analog VDD.
R-D3.3V
D16
LVDS_VDDD
—
LVDS Digital VDD.
R-D3.3V
C17, D17
LVDS_VDDO
—
LVDS out buffer VDD.
R-D3.3V
P20
NC
—
Not connected.
open
U1
AVDDAPLL
—
1.2V analog PLL power.
D1.2V
V1
AVSSAPLL
—
1.2V analog GND.
GND
R2
AVDDLLPLL
—
1.2V Line Lock PLL power.
D1.2V
T1
AVSSLLPLL
—
1.2V Line Lock PLL GND.
GND
Miscellaneous Ball Assignments.
F18
F18
RESET
I
System reset forces the chip to a known state. Active High. SVP_RESET
TO CPLD
G18
INTN
I/O
Interrupt signal (active low).
N_CPLD_INT
TO CPLD
G17
PWM0
I/O
PWM I/O. (no connected)
open
F16
V5SF
I
5V reference voltage (must be connected to 5V even in
standby mode, when CPU I/O is 5V)
standby mode, when CPU I/O is 5V)
D5V
F17
TESTMODE
I
Reserved (Connected to ground).
-
R-GND
LVDS Output Ball Assignments.
A14
A14
TA1P
O
LVDS 1st Channel Differential positive data out.
TA1+
TO LCD CONT
B14
TA1M
O
LVDS 1st Channel Differential negative data out.
TA1-
TO LCD CONT
A15
TB1P
O
LVDS 1st Channel Differential positive data out.
TB1+
TO LCD CONT
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
Destination
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