Read Sharp AR-P16 (serv.man3) Service Manual online
AR-P16 HARDWARE 5 - 3
Pin Assignment
(3) Engine I/F
Engine Interface is supported in PRTC (Alpha-5) board. There are a
power supply line, Video-related signals, Scanner-related signals, and
signals of communication relation with engine in this Engine Interface.
Moreover, Video-related signals and communication-related signals
are controlled by D8501A. Scanner-related signals are controlled by
SCNIF ASIC on the SCNIF board via PCI I/F.
power supply line, Video-related signals, Scanner-related signals, and
signals of communication relation with engine in this Engine Interface.
Moreover, Video-related signals and communication-related signals
are controlled by D8501A. Scanner-related signals are controlled by
SCNIF ASIC on the SCNIF board via PCI I/F.
(4) Clock
The XPC107 provides an on-chip delay-locked loop (DLL) that sup-
plies the external memory bus clock signals to SDRAM banks and also
supplies three CPU clock outputs that are synchronized to the SDRAM
clocks. The memory bus clock signals are of the same frequency and
synchronous with the processor clock signals.
plies the external memory bus clock signals to SDRAM banks and also
supplies three CPU clock outputs that are synchronized to the SDRAM
clocks. The memory bus clock signals are of the same frequency and
synchronous with the processor clock signals.
The MPC107's internal PLL is configured by the PLL_CFG[0-3] sig-
nals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configu-
ration signals set the Core/Memory/Processor PLL (VCO) frequency of
operation for the PCI-to-Core/Memory/Processor frequency multiply-
ing, if any. All valid PLL configurations for the MPC107 are shown in
the following table.
nals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configu-
ration signals set the Core/Memory/Processor PLL (VCO) frequency of
operation for the PCI-to-Core/Memory/Processor frequency multiply-
ing, if any. All valid PLL configurations for the MPC107 are shown in
the following table.
XPC107 PLL Configuration
No
．
Compatible
Nibble, Byte
ECP
No
．
Compatible,
Byte Nibble,
Byte Nibble,
ECP
1
Nstrobe
HostClk
HostClk
19
GND
2
D1
D1
D1
20
GND
3
D2
D2
D2
21
GND
4
D3
D3
D3
22
GND
5
D4
D4
D4
23
GND
6
D5
D5
D5
24
GND
7
D6
D6
D6
25
GND
8
D7
D7
D7
26
GND
9
D8
D8
D8
27
GND
10
Nack
PrtClk
PeriphClk
28
GND
11
Busy
PrtBusy
PriphAck
29
GND
12
Rerror
AckDatReq
nAckReverse
30
GND
13
Select
Xflag
Xflag
33
N.C
14
NautoFd
HostBusy
HostAck
34
N.C
15
N.C
N.C
N.C
35
N.C
16
GND
GND
GND
17
FGND
FGND
FGND
18
LogicHigh
LogicHigh
LogicHigh
31
Nlnit
Nlnit
NrserveReqyest
32
Nfault
NdataAvil
NperiphRequest
36
Nselection IEEE1284active IEEE1284active
Engine I/F
(CN1)
244 Buffer
(IC3-4,
IC6-7)
/CNTUP
/ENGUP
/CNTWU
/ENGWU
KD[3:0]
CD[3:0]
MD[3:0]
YD[3:0]
/KVSYNC
/CVSYNC
/MVSYNC
/YVSYNC
/KHSYNC
/CHSYNC
/MHSYNC
/YHSYNC
/TXD_PRT
/RXD_PRT
DTR_PRT
DSR_PRT
RES_PRT
RES_PCU
PWM
POF
ECLK
Video Data
(4bit/color)
(4bit/color)
Video Clock
Vertical
Synchronization
Synchronization
Horizontal
Synchronization
Synchronization
Communication
Signals
(GPIO)
Signals
(GPIO)
Engine Power
Status Signals
Status Signals
D8501A
(IC22)
VD3[3:0]
VD2[3:0]
VD1[3:0]
VD0[3:0]
ECLK[3:0]
VSYNCZ / INTX4
INTX10
INTX9
INTX8
HSYNC3
HSYNC2
HSYNC1
HSYNC0
GPIO15
GPIO14
RTSZ
CTSZ
GPIO13
GPIO28
TXD
RXD
GPIO9
GPIO30
INTX3
CNTUP
LCX14
ICUUP
DTC114YKA
ENGWU
DTC114YKA
LCX14
PRTCWU
RESPCUN
LCX14
Communication
Signals
(UART)
Signals
(UART)
CMD
LCX14
STS
/SRDY
LCX14
/CRDY
DTC114YKA
LCX14
/POF
LCX14
244 (IC7)
Fan Power CN
(CN12)
SCLK
SEL
244
Buffer
(IC9-10)
SOR[76, 54, 32, 10]
SOG[76, 54, 32, 10]
SOB[76, 54, 32, 10]
Fan PWM
Scanner
Data
(8bit/color)
Data
(8bit/color)
LD_GT
Scanner Control
Signals
Signals
Scanner Clock
SCNIF
Slot
(CN8)
SCNIF
Board
(N1521)
Ref
PLL_
CFG
[0-3]
PCI_SYNC_IN
Range (MHz)
Core/Mem/
CPURange
(MHz)
PCI: Core
Ratio
VCO
Multiplier
1
0001
25 - 50
25 - 50
x1
4
2
0010
12.5 - 25
25 - 50
x2
4
3
0011
Bypass
Bypass
Bypass
Bypass
5
0101
25 - 33
50 - 66
x2
2
8
1000
16 - 22
50 - 66
x3
2
9
1001
33 - 44
50 - 66
x1.5
2
C
1100
20 - 26
50 - 66
x2.5
2
D
1101
50 - 66
50 - 66
x1
2
F
1111
Clock off
Not usable
Off
Off
XTAL
(Y3)
16.345
MHz
XPC107
(IC40)
OSC_IN
CPU_CLK0
CPU_CLK1
CPU_CLK2
MPC755 (IC26)
D8501 (IC22)
D3032 (IC31)
PCI_CLK1
PCI_CLK2
PCI_CLK3
NIC (CN9)
HDD (CN12)
SCNIF (CN8)
66MHz
33MHz
SDRAM_CLK0
On Board SDRAM
(IC27, 32, 39, 46)
Zero
Delay
Buffer
(IC29)
66MHz
SDRAM_CLK1
4
4
DIMM #0 (CN10)
DIMM #1 (CN11)
66MHz
33MHz
33MHz
66MHz
66MHz
PCI_SYNC_OUT
PCI_SYNC_IN
33MHz
SDRAM_SYNC_OUT
SDRAM_SYNC_IN
66MHz
SS IC
(IC35)
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