Read Sharp TU-X1E (serv.man8) Service Manual online
TU-X1E/RU
7 – 4
[2] MAIN UNIT
1. VHISII9185+-1Q 3:1 HDMI 1.3 Switch
Pin No.
Pin Name
I/O
Pin Function
System Switching Pins
30,
50,
50,
70
DSDA0,
DSDA1,
DSDA1,
DSDA2
I/O
DDC I2C Data for respective port.
31,
51,
51,
71
DSCL0,
DSCL1,
DSCL1,
DSCL2
I
DDC I2C Clock for respective port.
32,
52,
52,
72
RPWR0,
RPWR1,
RPWR1,
RPWR2
I
5V Port detection input for respective port.
Connect to 5V signal from HDMI input connector.
Connect to 5V signal from HDMI input connector.
16,
36,
36,
56
HPD0,
HDP1,
HDP1,
HPD2
O
Hot Plug Detect Output for respective port.
Connect to HOTPLUG of HDMI input connector.
Connect to HOTPLUG of HDMI input connector.
76
HPDIN
I
Hot Plug Detect Input.
78
TSCL
O
Master DDC I2C Clock (Open Drain Output) to HDMI receiver.
I2C transactions required for HDCP operation are performed over this I2C bus.
I2C transactions required for HDCP operation are performed over this I2C bus.
77
TSDA
I/O
Master DDC Data (Open drain output.) to HDMI receiver. I2C transactions required
for HDCP operation are performed over this I2C bus.
for HDCP operation are performed over this I2C bus.
Configuration Pins
79
I2CADDR/ TPWR
I/O
I2C Slave Address input / Transmit Power Sense output pin.
When RESET# is low, this pin is used as an input to latch the I2C sub-address. The
level on this pin is latched when the RESET# pin transitions from low to high.
When RESET# is high, this pin is used as the TPWR output, indicating that the
selected Rx-port has 5V present. When none of the Rx ports are selected, this signal
is low.
When RESET# is low, this pin is used as an input to latch the I2C sub-address. The
level on this pin is latched when the RESET# pin transitions from low to high.
When RESET# is high, this pin is used as the TPWR output, indicating that the
selected Rx-port has 5V present. When none of the Rx ports are selected, this signal
is low.
35
I2CSEL/INT#
I/O
I2C Selection input / Interrupt output pin.
When RESET# is low, this pin is used as an input to latch the External Port Detection
signal. The level on this pin is latched when the RESET# pin transitions from low to
high. When this pin is low during reset, the external pins EPSEL1/LSCL and EPSEL0/
LSDA are used to select the Rx-port as EPSEL[1:0].
When this pin is high during reset, the internal local I2C register is used to select the
Rx-port.
When RESET# is low, this pin is used as an input to latch the External Port Detection
signal. The level on this pin is latched when the RESET# pin transitions from low to
high. When this pin is low during reset, the external pins EPSEL1/LSCL and EPSEL0/
LSDA are used to select the Rx-port as EPSEL[1:0].
When this pin is high during reset, the internal local I2C register is used to select the
Rx-port.
75
RSVDL
I
Reserved for use by Silicon Image and must be tied low.
Control Pins
13
RESET#
I
Reset Pin (Active LOW). Certain configuration inputs are latched when RESET# tran-
sitions from low to high.
sitions from low to high.
15
LSCL/EPSEL1
I
Local I2C Clock / External Port Select 1. When I2CSEL is high, this becomes the
Local I2C bus clock pin, LSCL. When I2CSEL is low, this becomes the external port
select pin, EPSEL1. True open drain, so does not pull to ground if power not applied.
An external pull-up is required.
Local I2C bus clock pin, LSCL. When I2CSEL is low, this becomes the external port
select pin, EPSEL1. True open drain, so does not pull to ground if power not applied.
An external pull-up is required.
14
LSDA/EPSEL0
I/O
Local I2C Data / External Port Select 0. When I2CSEL is high, this becomes the Local
I2C bus data pin, LSDA. When I2CSEL is low, this becomes the external port select
pin, EPSEL0. True open drain, so does not pull to ground if power not applied. An
external pull-up is required.
I2C bus data pin, LSDA. When I2CSEL is low, this becomes the external port select
pin, EPSEL0. True open drain, so does not pull to ground if power not applied. An
external pull-up is required.
CEC Pins
54
CEC_A
I/O
HDMI compliant CEC I/O used to interface to CEC devices.
CEC electrically compliant signal. This pin connects to the CEC signal of all HDMI
connectors in the system. As an input, the pad acts as a LVTTL Schmitt triggered
input and is 5V tolerant. As an output, the pad acts as an NMOS driver with resistive
pull-up. This pin has an internal pull-up resistor.
CEC electrically compliant signal. This pin connects to the CEC signal of all HDMI
connectors in the system. As an input, the pad acts as a LVTTL Schmitt triggered
input and is 5V tolerant. As an output, the pad acts as an NMOS driver with resistive
pull-up. This pin has an internal pull-up resistor.
53
CEC_D
I/O
CEC interface to local system. True open-drain. An external pull-up is required. This
pin typically connects to the local CPU.
pin typically connects to the local CPU.
Differential Signal Data Pins
22
R0X0+
I
TMDS input Port 0 data pairs.
21
R0X0-
I
25
R0X1+
I
24
R0X1-
I
28
R0X2+
I
27
R0X2-
I
19
R0C+
I
TMDS input Port 0 clock pair.
18
R0C-
I
Click on the first or last page to see other TU-X1E (serv.man8) service manuals if exist.