ER-A880 (serv.man2). ERA850 880 Service Manual - Sharp EPOS Service Manual (repair manual). Page 69

I

AST (Address strobe from DMAC), In
Pin 39
An input from the DMAC which is used to latch the information
from the DMAC Sent on the data bus with AST In the DMAC
cycle to create A8, A9, A10, and A15 address information.

J

DAK01 (DMA acknowledge 0+1), Input
Pin 22
The subsystem uses four DMA channels; one each for transmit-
ting and receiving of data (DAK0, DAK1), and for read and write
of received data (DAK2, DAK3), DAK01 is a logical OR of DAK0
with DAK1 which is used for DMA control of transmission data.

K

DAK23 (DMA acknowledge 2+3), Input
Pin 41
This signal is a logical OR of DAK2 and DAK3 and is used for
DMA control of transmission data.

L

DRQRS (DMA request read to sub CPU), Output
Pin 42
An active low DMA request to the sub CPU to read data which is
normally connected to the DMA controller of the sub.

M

DRQWS A request to write to sub CPU), Outut
Pin 43
An active low DMA request to the sub CPU to write data which is
normally connected to the DMA controller of the sub CPU.

N

TCS (Terminal count from sub), Input
Pin 40
An active high signal which the subsystem uses to inform that
the current DMA cycle is the final cycle.

O

INTS (Interrupt to sub), Input
Pin 17
An interrupt which the controller uses to inform the sub that it
has data to be read or written. This output is a half duty oscilla-
tion signal when active.

P

WAIT (Wait signal), Output
Pin 13
This signal is used to provide synchronization for the DMAC and
the sub CPU with the link controller (ADLC) when transferring
data with the link controller (ADLC), that is, to wrtie a command
to the ADLC, to read status, and to write or read transmit or
receive data. This line is normally an input to the DMAC and sub
CPU WAIT (ready) line.

Q

CLK (Clock input), Input
Pin 1
Basic frequency input which is used to derive system clock,
transmit/receive clock, and internal sync clock, [16MHz]

R

φ

 (clock out), Output

Pin 8
A system clock output which the basic oscillation is divided by
four, Since the basic frequency is normally at 16MHz, the system
clock output is a 4MHz.

S

TXC (Transmit clock), Output (for SRN)
Pin 71
As the basic frequency is divided 1/16 or 1/32, it is supplied as
the transmit clock for the SRN system.
Choice of 1/16 and 1/32 is dependent on the sub CPU.

T

TXD (Transmit data from ADLC), Input (for SRN)
Pin 72
Transmit data from the link controller (ADLC).

U

TDI (Transmit data to driver), Output (for SRN)
Pin 67 
Transmit data which TXD is phase encoded with the transmit
clock which is an input to the line driver of the SRN.

V

RDI (Receiver data from receiver), Input (for SRN)
Pin 66
Phase encoded data from the other end via the line receiver of
the SRN.

W

RXD (Receive data to ADLC), Input (for SRN)
Pin 70
Receive data (RXD) output as the phase encoded data from the
other end received via the receiver are demodulated within the
controller to separate it into the receive data (RXD) and receive
clock, which is normally an input to the link controller (ADLC).

X

RXC (Receive clock to ADLC), Output (for SRN)
Pin 69
An output of the receive clock (RXC) which is normally supplied
to the link controller (ADLC).

Y

RTS (Request to send), Input (for SRN)
Pin 68
An input from the link controller (ADLC) which becomes active
low during transmission. The controller uses it for controlling the
collision detect circuit and modem circuit.

Z

LCS (Link controller chip select), Output
Pin 76
A chip select signal for the link controller (ADLC) in which the
sub CPU synchronizes with the DMCA.

[

IRQ (Interrupt request from ADLC), Input
Pin 75
An Interrupt request from the link controller (ADLC).

\

E (Enable clock to ADLC), Input
Pin 74
Link controller (ADLC) enable clock which the sub CPU synchro-
nizes with the DMAC for data read to write.

]

RS0 (Register select 0), Outpt
Pin 79
Command and status register select signal for the link controller
(ADLC).

^

RS1 (Register select 1), Output
Pin 78
Command and status register select for the link controller
(ADLC) which is used in conjunction with RS0 above.

_

MSK (Mask signal), Output
Pin 80
Used to mask the signal to avoid DMA looping, except for other
than the data transmit/receive DMA request signal (input from
the link controller (ADLC), normally).

‘

COL (Collision detect signal), Input
Pin 65
To avoid collision on the line, the data sent, from this side are
compared with the data on the line. In other words, when the
data sent are equal to the on line, no collision is assumed. If not
equal, an occurrence of data collision is assumed. This line is,
therefore, the input of the data sent from this side.

a

TM0 (Timer 0), Input
Pin 9
A clock of a given interval (100 msec) sent from the subsystem’s
timer and counter. It is used to create the carrier off wait signal
and back-off timer within the controller.

b

TM1 (Timer 1), Output
Pin 10
Back-off timer output is a clock pulse ten times the TM0 fre-
quency (T1=10xT0), where T1 is TM 1 clock and T0 is a TM0
clock.

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