ER-A880 (serv.man2). ERA850 880 Service Manual - Sharp EPOS Service Manual (repair manual). Page 68

3

WRH (Write from sub), Input
Pin 45
An active low signal which is used when the host writes the
hardware flag and 8-bit data through the data bus.

4

CS (Chip select from host), Input
Pin 51
An active low signal which is used when the host reads or writes
the hardware flag and 8-bit data through the data bus.

5

AB0, AB1(Address bus from host), Input
Pin 62, 64
An input signal used to select the register when the host reads or
writes the hardware flag and 8-bit data through the data bus.

6

DAK (DMA Acknowledge from host), Input
Pin 47
Not used (+5v)

7

DRQRH (DMA Request read to host), Output
Pin 49
Not used

8

DRQWH (DMA request write to host), Output
Pin 50
Not used

9

TCH (Terminal count from host), Input
Pin 48
Not used

F 

INTH (Interrupt to host), Output
Pin 46
An active low signal which is used to inform the interrupt signal
that the controller has the information to read or write.

G

RES (Reset), Input
Pin 35
Asynchronous reset signal from the host which is used to reset
registers within the controller.

•

HOST read timing.

Fig. 8

•

HOST write timing.

Fig. 9

1

D0 – D7 (Data bus) Input Output (3-state)
Pin 32 – 25
These lines (data bus) are used for hardware flag assignments:
8 bit data write, hardware flag recognition, and 8-bit data read
from the subsystem.

2

IORQ (I/O request), Input
Pin 3
An active low memory request input from the subsystem (Z-80A)
which is used to create I/O control signals in conjunciton with
RDS, WRS, A0, A1, A4 and A5.

3

MREQ (Memory request), Input
Pin 4
An active low memory request input from the subsystem (Z-80A)
which is used to create I/O control signals in conjunction with
RDS and WRS.

4

RDS (Read from sub), Input
Pin 5
Data read signal received from the subsystem (Z-80A) wihch is
used to create I/O and memory data read control signal.

5

WRS (Write from sub), Input
Pin 6 
Data write signal received from the subsystem (Z-80A) which is
used to create I/O and memory data write control signal.

6

MRD (Memory read), Output
Pin 11
Memory data read control signal sent to the subsystem (mem-
ory) which is created with MREQ and RDS.

7

MWRO (Memory write), Output
Pin 24
Memory data write control signal sent to the subsystem (mem-
ory) which is created with MREQ and RDS.

8

IO/WR (I/O write), Input/Output (3-state)
Pin 36
I/O data write control signal sent to the subsystem (peripheral
I/O) which is created with IORQ And WRS.
During the DMA mode, it is received from the DMAC to create
the memory  to I/O data transfer control signal.

9

IO/RD (I/O read), Input/Output (3-state)
Pin 37
I/O data read control signal sent to the subsysystem (peripheral
I/O) which is created with IORQ and WRS. During the DMA
mode, it is received from the DMAC to create the I/O to memory
data transfer control signal.

F

AO, A1, A4, A5 (Address bus from sub CPU), In
Pin 21, 20, 19, 18
An input signal used to create the selection signal which the sub
reads the hardware flag and subsystem  (peripheral I/O) 8-bit
data through the data bus.

G

A8, A9, A10, A15 (Address bus for DMA), Output (3-state)
Pin 17, 16, 15, 14
Used to create the memory address information on the basis of
the information from the DMAC during the DMA cycle. The out-
put has 3-stats and retains a high impedance except during the
DMA cycle.

H

AEN (Address enable from DMAC), In
Pin 38
An input from the DMAC which is used to enable the DMAC to
control by isolating the system address bus from the CPU (Z-
80A) during the DMA cycle.
That is, A8, A9, A10, and A15 are set to output condition from
their high impedance state.

CS

AB0, AB1

RDH

DB0-DB7

TAR

TRWS

TRA

TRDE

TRDF

CS

AB0, AB1

WRH

DB0-DB7

TAW

TWWS

TWA

TDW

TWD

– 64 –