DV-720H (serv.man19). IC Function List - Sharp DVD Service Manual (repair manual). Page 10

CD-DSP Interface (4 pins)

Pin No.

Pin name

Type

Direction

Function

3

CDERR

I

I/O (r.t.)

Reset: input (p.d.)

4

CDFRM

I

I/O (r.t.)

Standby: 3-S (p.d.)

5

CDDAT

I

I/O (r.t.)

6

CDCLK

I

I/O (r.t.)

When HWID is connected to GNDP, these are the CD-DSP I

2

S input port pins as follows:

CDERR: data error indication input
CDFRM: left/right channel frame input
CDDAT: data input
CDCLK: bit clock input
When HWID is connected to VDDP, these are HD[15:12] of the host data bus, as explained in the host interface pin
description.

Digital Video Interface (16 pins)

Pin No.

Pin name

Type

Direction

Function

98

VID[7]

3-S

I/O (r.t.)

Reset: 3-S

99

VID[6]

3-S

I/O (r.t.)

Standby: 3-S (p.d.)

100

VID[5]

3-S

I/O (r.t.)

101

VID[4]

3-S

I/O (r.t.)

103

VID[3]

3-S

I/O (r.t.)

105

VID[2]

3-S

I/O (r.t.)

107

VID[1]

3-S

I/O (r.t.)

108

VID[0]

3-S

I/O (r.t.)

Digital video luminance/chrominance outputs, multiplexed in time according to the CCIR656 standard. Used (with
HSYNC and VSYNC) as 10 bits input DACs testing.

140

VCLKx2

3-S

I/O (r.t.)

Reset:
Standby: 3-S (p.d.)

Main video clock input or output. 27.000MHz.

89

VCLK

3-S

I/O (r.t.)

Reset:
Standby: 3-S (p.d.)

A division by two of the VCLKx2 signal. This signal is used as data and sync qualifier.

95

HSYNC

3-S

I/O (r.t.)

Reset:
Standby: 3-S (p.d.)

Horizontal sync input/output. Polarity and duration are programmable.

93

VSYNC

3-S

I/O (r.t.)

Reset:
Standby: 3-S (p.d.)

Vertical sync input/output. Polarity and duration are programmable.

96

FI

3-S

I/O (r.t.)

Reset:
Standby: 3-S (p.d.)

Field indication input/output. Polarity is programmable.

92

CBLANK

O

O (p.d.)

Reset: output
Standby: 3-S (p.d.)

Composite blank output. Horizontal and vertical blanking areas and polarity are programmable.

90

VMASTER

I

I

Input

Video master/slave selection input. When this input is high, the Decoder is the video sync master (video SYNC
signals and clocks are output). When it is low, the Decoder is a video Sync slave (video SYNC signals and clocks are
input). This input may be changed only during RESET.

91

VDEN#

I

I

Input

Video enable input. When this input is active, the Decoder may output video data on the VID[[7:0] bus. When it is
deasserted, the Decoder tri-states the VID[7:0] bus outputs (although the sync signals are still active). This input may
be changed dynamically and if affects at the next VCLKx2.

Analog Video Encoder Interface (8 pins)

Pin No.

Pin name

Type

Direction

Function

114

CVBS/G/Y

O

AO

Reset:

(DAC A)

Standby: 3-S

When the Decoder outputs composite video, this line is CVBS
When the Decoder outputs RGB, this line is the Green output
When the Decoder outputs YUV, this line is the U output