DV-720H (serv.man19). IC Function List - Sharp DVD Service Manual (repair manual). Page 8

Reset, Standby and Idle Status Interface (3 pins)

Pin No.

Pin name

Type

Direction

Function

137

RESET#

I

I

Input

Reset input. Once de-asserted, the Decoder starts the initialization process.

136

STNBY#

I

I

Input

Stand-by input. When asserted together with RESET#, all outputs and bidirectional pins float, such that the Decoder
is electrically disconnected from its surroundings. All internal clocks are disabled, and the power consumption is
minimized.

174

IDLE

3-S

O (p.u.)

Reset: output (high)
Standby: 3-S (p.u.)

Idle, Init and Reset states indication output.

Host Interface (29 pins)

Pin No.

Pin name

Type

Direction

Function

176

HWID

I

I

Input

Determines the width of the host interface data bus. It is allowed to be changed only during RESET.
A low level (GNDP) configures the Decoder to 2- or 8-bit host data interface, a high level (VDDP) to 16-bit width.

175

HORD

I

I

Input

Determines the order of bytes on the host interface data bus in case of 16-bit width (HWID at VDDP). It is allowed to
be changed only during RESET. A low level (GNDP) configures the Decoder to input/output the m.s. byte on
HD[15:8], a high level (VDDP)to input/output the m.s. byte on HD[7:0]. If HWID is at GNDP level, this input is use to
select between the 2-bits mode (VDDP) and 8-bits mode (GNDP)

2

HTYPE

I

I

Input

Determines the protocol type for the 8 and 16 bits modes host interface. It is allowed to be changed only during
RESET. A low level (GNDP) configures the Decoder to type A, a high level (VDDP) to type B.

15

HD[7]

3-S

I/O (r.t.)

Reset: input (p.d.)

16

HD[6]

3-S

I/O (r.t.)

Standby: 3-S (p.d.)

17

HD[5]

3-S

I/O (r.t.)

18

HD[4]

3-S

I/O (r.t.)

19

HD[3] —HVCTL

3-S

I/O (p.u.)

20

HD[2] —HVAD[1]

3-S

I/O (r.t.)

21

HD[1] —HVAD[2]

3-S

I/O (r.t.)

22

HD[0] —HVCLK

3-S

I/O (p.u.)

For 16 bits mode, the 8 l.s. data lines of host data bus. For 8 bits mode, only these signals are defined as host data
signals. For 2 bits mode only 4 lines are used:
HVCTL—Host VIP mode control signal
HVAD[1:0]—Host VIP mode address/data bus
HVCLK— Host VIP mode clock.

7

HD[11]

3-S

I/O (p.d.)

Reset: input (p.d.)

9

HD[10]

I/O (r.t.)

Standby: 3-S (p.d.)

11

HD[9]

I/O (r.t.)

13

HD[8]

I/O (r.t.)

When HWID is connected to VDDP, these are data lines 11:8 of the 16-bit host data bus.

3

HD[15]

3-S

I/O (r.t.)

Reset: input (p.d.)

4

HD[14]

I/O (r.t.)

Standby: 3-S (p.d.)

5

HD[13]

I/O (r.t.)

6

HD[12]

I/O (r.t.)

When HWID is connected to VDDP, these are data lines 15:12 of the 16-bit host data bus. When HWID is connected
to GNDP, these are the CD-DSP I

2

S input port pins, as explained in the CD-DSP pin description.

24

HA[3]

I

I

Input

25

HA[2]

I

I

26

HA[1]

I

I

27

HA[0]

I

I

Host address inputs. These input signals indicate the register accessed in every cycle on the host interface.

29

HCS#

I

I

Input

Host chip-select input.

28

HWR#—HR/W#

I

I

Input

In host protocol type A (HTYPE=GNDP):HR/W#. This input determines the direction of the host access.
In host protocol type B (HTYPE=VDDP):HWR#. Host write input.