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SD-CX1H
DESCRIPTION OF CIRCUIT FOR 1-BIT AMP. UNIT
(SEE THE WIRING DIAGRAMS ON PAGES 52 AND 53.)
Input
Signals over certain level input from BIA106 are sliced into waveforms by RA173 (RA174), DA126, and DA127 (DA128, DA129).
The slice levels depend on the output of the unit.
In case of 25 W output setting, the level is set to gain distortion of approx. 10 % during output.
The level on the positive side is determined by RA175, RA177 and RA179 and that on the negative side by RA176, RA178, and
RA180, respectively.
After DC cut by CA108, the signals are input to AD conversion IC.
Signals over certain level input from BIA106 are sliced into waveforms by RA173 (RA174), DA126, and DA127 (DA128, DA129).
The slice levels depend on the output of the unit.
In case of 25 W output setting, the level is set to gain distortion of approx. 10 % during output.
The level on the positive side is determined by RA175, RA177 and RA179 and that on the negative side by RA176, RA178, and
RA180, respectively.
After DC cut by CA108, the signals are input to AD conversion IC.
modulation 1-bit conversion
The signals input to the AD conversion IC are converted into 1-bit signals for differential output.
For detailed technical description of 1-bit signal conversion, refer the technical manual for SM-SX100 already published.
The signals input to the AD conversion IC are converted into 1-bit signals for differential output.
For detailed technical description of 1-bit signal conversion, refer the technical manual for SM-SX100 already published.
Dead time and level shift
When the 1-bit signals are output from the AD conversion IC, the leading edge of the waveform is delayed for 20 to 25 nsec by
DA103 (DA102, DA101, and DA100), RA115 (RA114, RA113, and RA112), and CA155 (CA154, CA153, and CA152), compared
with the trailing edge.
As mentioned below, this operation is for reducing switching circuit loss in the final stage.
The signals are input to the buffer IC (AND gate IC) for the waveform format and are output.
Then the DC level is shifted by CA115 (CA114, CA113, and CA112), DA107 (DA106, DA105, and DA104) and RA120 (RA119,
RA118, and RA117). This is because the buffer IC operates between ground and + 5 V, while the next stage IC, gate driver (ICA101
to ICA 104), operates between the negative power source and + 9 V.
The shift quantity is output with amplitude of 5 V, based on the voltage raised by DA108 and DA109 from the bottom by approx.
2 V.
When the 1-bit signals are output from the AD conversion IC, the leading edge of the waveform is delayed for 20 to 25 nsec by
DA103 (DA102, DA101, and DA100), RA115 (RA114, RA113, and RA112), and CA155 (CA154, CA153, and CA152), compared
with the trailing edge.
As mentioned below, this operation is for reducing switching circuit loss in the final stage.
The signals are input to the buffer IC (AND gate IC) for the waveform format and are output.
Then the DC level is shifted by CA115 (CA114, CA113, and CA112), DA107 (DA106, DA105, and DA104) and RA120 (RA119,
RA118, and RA117). This is because the buffer IC operates between ground and + 5 V, while the next stage IC, gate driver (ICA101
to ICA 104), operates between the negative power source and + 9 V.
The shift quantity is output with amplitude of 5 V, based on the voltage raised by DA108 and DA109 from the bottom by approx.
2 V.
Output of gate driver
The level-shifted signals are input to the gate driver IC (HIP2100).
Since the final stage FET array is H bridge, two gate drivers are used for 1 CH.
At this time, + and - of differential signals are input by crossing diagonally for the two gate drivers.
(Positive output to ICA101 (ICA103) Hin and ICA102 (ICA104) Lin, and negative output to ICA102 (ICA104) Hin and ICA101
(ICA103) Lin.)
Output of the gate driver drives the gate of FET array connected to H bridge.
FET consists of the lower stage where source is connected to the negative power and the upper stage where drain is connected
to the positive power. Lout and Hout are connected to the gate, respectively.
The lower stage FET is driven with 9 V amplitude based on the negative power because the reference voltage is same as in the
gate driver. The upper stage FET does not operate as it is because it is based on the positive power. Therefore this gate drive IC
(HIP2100) makes up bootstrap, by feeding back from FET output.
As a result, amplitude of Hout is approx. + 6V of the positive power, based on the negative power.
The level-shifted signals are input to the gate driver IC (HIP2100).
Since the final stage FET array is H bridge, two gate drivers are used for 1 CH.
At this time, + and - of differential signals are input by crossing diagonally for the two gate drivers.
(Positive output to ICA101 (ICA103) Hin and ICA102 (ICA104) Lin, and negative output to ICA102 (ICA104) Hin and ICA101
(ICA103) Lin.)
Output of the gate driver drives the gate of FET array connected to H bridge.
FET consists of the lower stage where source is connected to the negative power and the upper stage where drain is connected
to the positive power. Lout and Hout are connected to the gate, respectively.
The lower stage FET is driven with 9 V amplitude based on the negative power because the reference voltage is same as in the
gate driver. The upper stage FET does not operate as it is because it is based on the positive power. Therefore this gate drive IC
(HIP2100) makes up bootstrap, by feeding back from FET output.
As a result, amplitude of Hout is approx. + 6V of the positive power, based on the negative power.
Low-pass filter circuit
1-bit signals switched at FET are converted into analog signals via the low-pass filter consisting of LA100 (LA102, LA104, and
LA106) and CA142 (CA143, CA150, and CA151).
Property of the low-pass filter is flat up to 20 kHz and then is attenuated by approx. 3 dB at around 30 kHz.
1-bit signals switched at FET are converted into analog signals via the low-pass filter consisting of LA100 (LA102, LA104, and
LA106) and CA142 (CA143, CA150, and CA151).
Property of the low-pass filter is flat up to 20 kHz and then is attenuated by approx. 3 dB at around 30 kHz.
Dynamic feedback circuit
1-bit signals switched at FET of output stage are amplified between the positive and negative power sources.
With resistance divided, 1-bit signals are fed back to AD conversion IC, via NF resistance 75 kohms.
P-P voltage, which becomes approx. 4 to 7V, is determined by the regulation property of the transformer depending on the output
level.
1-bit signals switched at FET of output stage are amplified between the positive and negative power sources.
With resistance divided, 1-bit signals are fed back to AD conversion IC, via NF resistance 75 kohms.
P-P voltage, which becomes approx. 4 to 7V, is determined by the regulation property of the transformer depending on the output
level.
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