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SD-AT50H
– 48 –
41
RX2
Input
Receiver channel input 2 pin. (Internal bias pin)
42
I
2
C
Input
Serial control mode selection pin. “L” : 4-line serial, “H” : I2C bus
43
RX1
Input
Receiver channel input 1 pin. (Internal bias pin)
44
PDN
Input
Power down & reset pin.
When this pin is set to “L”, it falls into power down state; all the output pins change to “L”
and the register is initialized. If CAD1-0 is switched, reset it using the PDN pin.
and the register is initialized. If CAD1-0 is switched, reset it using the PDN pin.
IC102 VHiAK4586VQ-1: ADC/DAC/DIR Converter (AK4586VQ) (2/2)
Terminal Name
Pin No.
Input/Output
Function
Figure 48 BLOCK DIAGRAM OF IC
Notes :
1. Grouping of the channels can be set with DZFM2-0 bit.
2. This pin turns to an OVF pin if the OVFE bit is set to “1”.
3. Except for the internal bias pins, any of the digital input pins must not be floated.
1. Grouping of the channels can be set with DZFM2-0 bit.
2. This pin turns to an OVF pin if the OVFE bit is set to “1”.
3. Except for the internal bias pins, any of the digital input pins must not be floated.
1
XTO
XTI/EXTCLK
DVDD
DVSS
TVDD
TX
MCKO
LRCK
BICK
SDTO
SDTI1
RIN
LIN
LOUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
DZF1
VCOM
VREFH
SDTI2
SDTI3
INT0
INT1
CAD1/CDTO
SDA/CDTI
SCL/CCLK
CAD0/CSN
DZF2/OVF
AVSS
AVDD
ODN
RX1
I2C
RX2
TST
RX3
SLAVE
RX4
PVSS
R
PVDD
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
IC102
AK4586VQ
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