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SD-AT50H
25
SCLKN1, STCCLK2
Input
Bidirectional digital-audio bit clock that is an output in master mode and an input
in slave mode. In slave mode, SCLKN1 operates asynchronously from all other
CS493XX clocks. In master mode, SCLKN1 is derived from the CS493XX
internal clock generator. In either master or slave mode, the active edge of
SCLKN1 can be programmed by the DSP. For applications supporting PES layer
synchronization this pin can be used as STCCLK2, which provides a path to the
internal STC 33 bit counter.
in slave mode. In slave mode, SCLKN1 operates asynchronously from all other
CS493XX clocks. In master mode, SCLKN1 is derived from the CS493XX
internal clock generator. In either master or slave mode, the active edge of
SCLKN1 can be programmed by the DSP. For applications supporting PES layer
synchronization this pin can be used as STCCLK2, which provides a path to the
internal STC 33 bit counter.
26
LRCLKN1
Input
Bidirectional digital-audio frame clock that is an output in master mode and an
input in slave mode. LRCLKN1 typically is run at the sampling frequency.
In slave mode, LRCLKN1 operates asynchronously from all other CS493XX clocks.
In master mode, LRCLKN1 is derived from the CS493XX internal clock generator.
In either master or slave mode, the polarity of LRCLKN1 for a particular
subframe can be programmed by the DSP.
input in slave mode. LRCLKN1 typically is run at the sampling frequency.
In slave mode, LRCLKN1 operates asynchronously from all other CS493XX clocks.
In master mode, LRCLKN1 is derived from the CS493XX internal clock generator.
In either master or slave mode, the polarity of LRCLKN1 for a particular
subframe can be programmed by the DSP.
27
CMPDAT, SDATAN2
Input
Digital-audio data input that can accept from one to six channels of compressed
or PCM data. SDATAN2 can be sampled with either edge of SCLKN2, depending
on how SCLKN2 has been configured. Similarly CMPDAT is the compressed
data input pin when the CDI is configured for bursty delivery. When in this mode,
the CS493XX internal PLL is driven by the clock recovered from the incoming
data stream.
or PCM data. SDATAN2 can be sampled with either edge of SCLKN2, depending
on how SCLKN2 has been configured. Similarly CMPDAT is the compressed
data input pin when the CDI is configured for bursty delivery. When in this mode,
the CS493XX internal PLL is driven by the clock recovered from the incoming
data stream.
28
CMPCLK, SCLKN2
Input
Bidirectional digital-audio bit clock that is an output in master mode and an input
in slave mode. In slave mode, SCLKN2 operates asynchronously from all other
CS493XX clocks. In master mode, SCLKN2 is derived from the CS493XX
internal clock generator. In either master or slave mode, the active edge of
SCLKN2 can be programmed by the DSP. If the CDI is configured for bursty
delivery, CMPCLK is an input used to sample CMPDAT.
in slave mode. In slave mode, SCLKN2 operates asynchronously from all other
CS493XX clocks. In master mode, SCLKN2 is derived from the CS493XX
internal clock generator. In either master or slave mode, the active edge of
SCLKN2 can be programmed by the DSP. If the CDI is configured for bursty
delivery, CMPCLK is an input used to sample CMPDAT.
29
CMPREQ, LRCLKN2
Input
When the CDI is configured as a digital audio input, this pin serves as a
bidirectional digital-audio frame clock that is an output in master mode and an
input in slave mode. LRCLKN2 typically is run at the sampling frequency.
In slave mode, LRCLKN2 operates asynchronously from all other CS493XX
clocks. In master mode, LRCLKN2 is derived from the CS493XX internal clock
generator. In either master or slave mode, the polarity of LRCLKN2 for a
particular subframe can be programmed by the DSP.
When the CDI is configured for bursty delivery, or parallel audio data delivery is
being used, CMPREQ is an output which serves as an internal FIFO monitor.
CMPREQ is an active low signal that indicates when another block of data can
be accepted.
bidirectional digital-audio frame clock that is an output in master mode and an
input in slave mode. LRCLKN2 typically is run at the sampling frequency.
In slave mode, LRCLKN2 operates asynchronously from all other CS493XX
clocks. In master mode, LRCLKN2 is derived from the CS493XX internal clock
generator. In either master or slave mode, the polarity of LRCLKN2 for a
particular subframe can be programmed by the DSP.
When the CDI is configured for bursty delivery, or parallel audio data delivery is
being used, CMPREQ is an output which serves as an internal FIFO monitor.
CMPREQ is an active low signal that indicates when another block of data can
be accepted.
30
CLKIN
Input
CS493XX clock input. When in internal clock mode (CLKSEL == DGND), this
input is connected to the internal PLL from which all internal clocks are derived.
When in external clock mode (CLKSEL == VD), this input is connected to the
DSP clock.
input is connected to the internal PLL from which all internal clocks are derived.
When in external clock mode (CLKSEL == VD), this input is connected to the
DSP clock.
31
CLKSEL
Input
This pin selects the clock mode of the CS493XX.
When CLKSEL is low, CLKIN is connected to the internal PLL from which all
internal clocks are derived. When CLKSEL is high CLKIN is connected to DSP
clock.
When CLKSEL is low, CLKIN is connected to the internal PLL from which all
internal clocks are derived. When CLKSEL is high CLKIN is connected to DSP
clock.
32, 33
FILT2, FILT1
—
Connects to an external filter for the on-chip phase-locked loop.
34
VA
Input
Analog positive supply for clock generator. Nominally +2.5 V.
35
AGND
—
Analog ground for clock generator PLL.
36
RESET
Input
Asynchronous active-low master reset input. Reset should be low at power-up to
initialize the CS493XX and to guarantee that the device is not active during initial
power-on stabilization periods. As the rising edge of reset the host interface mode
is selected contingent on the state of the RD, WR and PSEL pins. Additionally,
an autoboot sequence can be initiated if a serial control mode is selected and
ABOOT is held low. If reset is low all bidirectional pins are high impedance inputs.
initialize the CS493XX and to guarantee that the device is not active during initial
power-on stabilization periods. As the rising edge of reset the host interface mode
is selected contingent on the state of the RD, WR and PSEL pins. Additionally,
an autoboot sequence can be initiated if a serial control mode is selected and
ABOOT is held low. If reset is low all bidirectional pins are high impedance inputs.
37, 38
DD, DC
—
This pin is reserved and should be pulled up with an external 4.7 k resistor.
39, 40
AUDATA2, AUDATA1
Output
PCM multi-format digital-audio data output, capable of two-channel 20-bit output.
This PCM output defaults to DGND as output until enabled by the DSP software.
This PCM output defaults to DGND as output until enabled by the DSP software.
41
AUDATA0
Output
PCM multi-format digital-audio data output, capable of two-, four-, or six-channel
20-bit output. This PCM output defaults to DGND as output until enabled by the
DSP software.
20-bit output. This PCM output defaults to DGND as output until enabled by the
DSP software.
42
LRCLK
Input
Bidirectional digital-audio output-sample-rate clock. LRCLK can be an output that
is divided from MCLK to provide the output sample rate depending on the output
configuration. LRCK can also be an input. As an input LRCLK is independent of
configuration. LRCK can also be an input. As an input LRCLK is independent of
MCLK.
IC101 VHiCS493264-1: DSP (CS493264) (2/3)
Pin No.
Function
Terminal Name
Input/Output
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