Read Panasonic KX-TCD951GB / KX-TCD955GC Service Manual online
63
KX-TCD951GB/KX-TCD955GC
49
B4
EMC (LSB)
Equipment Manufacturer Code
4A
00
EMC (MSB)
Equipment Manufacturer Code
BMC control variables
4B
80
Frequency
Default adjustment value for the crystal.
4C
2F
BMC.SyncCfg
RC0: S_err[3..0],INV_RDI,INV_TDO,SenseA,PP/Fpn
Bit 7..4 : S_err[3..0]. Max. number of allowed in
unmasked
S-fields bits.
00000 = 0 errors allowed
00001 = 1 error allowed
....
11111 = 15 errors allowed
Bit 3: inv_RDI. 1=invert incoming data on RDI pin
Bit 2: inv_TDO. 1=invert outgoing data on TDO pin
Bit 1: SenseA. If 1 B-field data is not written if CRC
error.
Bit 7..4 : S_err[3..0]. Max. number of allowed in
unmasked
S-fields bits.
00000 = 0 errors allowed
00001 = 1 error allowed
....
11111 = 15 errors allowed
Bit 3: inv_RDI. 1=invert incoming data on RDI pin
Bit 2: inv_TDO. 1=invert outgoing data on TDO pin
Bit 1: SenseA. If 1 B-field data is not written if CRC
error.
Bit 0: PP/Fpn. 1=PP mode
4D
00
BMC.MaskSlide
RC1: Slide[3..0], Mask[3..0]
Bit 7..4: Masking 1111= S[8..15]
Bit 3..0: Slide error measurement : 0000=none of
S[8..15]
Bit 7..4: Masking 1111= S[8..15]
Bit 3..0: Slide error measurement : 0000=none of
S[8..15]
4E
12
BMC.CM_Vol
RC2:
Bit 7: CM5. Test bit. 0=normal mode
Bit 6: CM6. Test bit. 0=normal mode
Bit 5..0: Vol[5..0]. Voltage level of Gaussian output on
TDO pin.
00000 = -6 dB
10000 = 0 dB
11111 = +6dB
Bit 7: CM5. Test bit. 0=normal mode
Bit 6: CM6. Test bit. 0=normal mode
Bit 5..0: Vol[5..0]. Voltage level of Gaussian output on
TDO pin.
00000 = -6 dB
10000 = 0 dB
11111 = +6dB
4F
FF
BMC.Comparator
RC3: Comparator Level. Valid range is 0..3fh or ffh.
Bit 7: 0 (overruled by software)
Bit 6: TM_ANA. Test bit - 0=normal mode
Bit 5..0: DAC output
Specifying FF will cause the software not to set
RC3.DON causing the DAC not to be active i.e. not to
be used. In case the DAC is not used the CMPREF
level must be supplied externally.
Bit 7: 0 (overruled by software)
Bit 6: TM_ANA. Test bit - 0=normal mode
Bit 5..0: DAC output
Specifying FF will cause the software not to set
RC3.DON causing the DAC not to be active i.e. not to
be used. In case the DAC is not used the CMPREF
level must be supplied externally.
50
5F
BMC.AdpWin
RC4: DPLL[2..0],ADP,WIN[3..0]
Bit 7..5: dpll tuning bits. "100" for best performance ?
Bit 4 : ADP. Adjust Phase bit
Bit 3..0 : WIN[3..0]. S-field bit window.
Bit 7..5: dpll tuning bits. "100" for best performance ?
Bit 4 : ADP. Adjust Phase bit
Bit 3..0 : WIN[3..0]. S-field bit window.
51
41
BMC.RC5
RC5:
Bit 7 : ENCoff, encryption on=?, off= .
Bit 6 : SenseS, if 1 and no S-field is detected no A/B
field data is written
Bit 5 : Ron. Test-bit. 0=normal mode
Bit 4 : Mutelevel. B_BTFM instruction will replace data
with the value of this bit
Bit 3 : SCoff . Scrambling of A+B fields 0=on, 1=off.
Bit 2 : DOFr. If CMPREF voltage is retrieved from ext.
sample & hold PD1 is used to synchronise.
DOFr determines when synchronisation takes
place.
Bit 7 : ENCoff, encryption on=?, off= .
Bit 6 : SenseS, if 1 and no S-field is detected no A/B
field data is written
Bit 5 : Ron. Test-bit. 0=normal mode
Bit 4 : Mutelevel. B_BTFM instruction will replace data
with the value of this bit
Bit 3 : SCoff . Scrambling of A+B fields 0=on, 1=off.
Bit 2 : DOFr. If CMPREF voltage is retrieved from ext.
sample & hold PD1 is used to synchronise.
DOFr determines when synchronisation takes
place.
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