Read Sony MEX-BT5100 Service Manual online
MEX-BT5100
53
IT BOARD IC511 HD6417727F100CV (BLUETOOTH CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
VCC-RTC
-
Power supply terminal (+1.9V)
2
XTAL2
I
System clock input terminal for internal real time clock Not used
3
EXTAL2
O
System clock output terminal for internal real time clock Not used
4
VSS-RTC
-
Ground terminal
5, 6
MD1, MD2
I
Setting terminal for the clock mode
7
NMI
I
Non-maskable interrupt input terminal Fixed at "H" in this set
8
IRQ0
I
Interrupt request signal input terminal Not used
9, 10
UART_INTA, UART_
INTB
I
Interrupt request signal input from the data bus interface
11, 12
IRQ3, IRQ4
I
Interrupt request signal input terminal Not used
13
VEPWC
O
Not used
14
VCPWC
O
Not used
15
MD5
I
Setting terminal for the endian
16
BREQ
I
Bus request signal input terminal Not used
17
BACK
O
Bus acknowledge signal output terminal Not used
18
VSSQ
-
Ground terminal
19
SD_CLK
O
Serial data transfer clock signal output to the data bus interface
20
VCCQ
-
Power supply terminal (+3.3V)
21 to 28
D31 to D24
I/O
Two-way data bus with the SD-RAM
29
VSSQ
-
Ground terminal
30
D23
I/O
Two-way data bus with the SD-RAM
31
VCCQ
-
Power supply terminal (+3.3V)
32 to 34
D22to D20
I/O
Two-way data bus with the SD-RAM
35
VSS
-
Ground terminal
36
D19
I/O
Two-way data bus with the SD-RAM
37
VCC
-
Power supply terminal (+1.9V)
38 to 40
D18 to D16
I/O
Two-way data bus with the SD-RAM
41
D15
I/O
Two-way data bus with the SD-RAM and fl ash ROM
42
VSSQ
-
Ground terminal
43
D14
I/O
Two-way data bus with the SD-RAM and fl ash ROM
44
VCCQ
-
Power supply terminal (+3.3V)
45 to 50
D13 to D8
I/O
Two-way data bus with the SD-RAM and fl ash ROM
51, 52
D7, D6
I/O
Two-way data bus with the SD-RAM, fl ash ROM and data bus interface
53
VSSQ
-
Ground terminal
54
D5
I/O
Two-way data bus with the SD-RAM, fl ash ROM and data bus interface
55
VCCQ
-
Power supply terminal (+3.3V)
56 to 60
D4 to D0
I/O
Two-way data bus with the SD-RAM, fl ash ROM and data bus interface
61
A0
O
Address signal output to the data bus interface
62
A1
O
Address signal output to the fl ash ROM and data bus interface
63
A2
O
Address signal output to the SD-RAM, fl ash ROM and data bus interface
64
VSSQ
-
Ground terminal
65
A3
O
Address signal output to the SD-RAM and fl ash ROM
66
VCCQ
-
Power supply terminal (+3.3V)
67 to 74
A4 to A11
O
Address signal output to the SD-RAM and fl ash ROM
75
VSSQ
-
Ground terminal
76
A12
O
Address signal output to the SD-RAM and fl ash ROM
77
VCCQ
-
Power supply terminal (+3.3V)
78, 79
A13, A14
O
Address signal output to the SD-RAM and fl ash ROM
80 to 85
A15 to A20
O
Address signal output to the fl ash ROM
86
VSSQ
-
Ground terminal
87
A21
O
Address signal output to the fl ash ROM
88
VCCQ
-
Power supply terminal (+3.3V)
89, 90
A22, A23
O
Address signal output terminal Not used
91
VSS
-
Ground terminal
92
A24
O
Address signal output terminal Not used
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