STR-KIV300 - Sony Audio Service Manual (repair manual). Page 63

N7

A12

I

Address inputs: Provided the row address for active commands and the column address 
for Read/Write commands to select one location out of the memory array in the respective 
bank. The address inputs also provide the op-code during Mode Register Set commands.
Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop (on-
the-fl y) will be performed. (HIGH: no burst chop, LOW: burst chopped).

N8

BA1

I

Bank Adress Inputs: BA1 defi ne to which bank an Active, Read, Write or Precharge command 
is being applied. Bank address also determines if the mode register or extended mode register 
is to be accessed during a MRS cycle.

N9

VDD

-

Power Supply: 1.5V +/-0.075

P1

VSS

-

Ground

P2

A5

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

P3

A2

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

P4

NO_USE

-

Not used

P5

NO_USE

-

Not used

P6

NO_USE

-

Not used

P7

A1

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

P8

A4

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

P9

VSS

-

Ground

R1

VDD

-

Power Supply: 1.5V +/-0.075

R2

A7

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

R3

A9

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

R4

NO_USE

-

Not used

R5

NO_USE

-

Not used

R6

NO_USE

-

Not used

R7

A11

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

R8

A6

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

R9

VDD

-

Power Supply: 1.5V +/-0.075

T1

VSS

-

Ground

T2

RESET

I

Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when 
RESET is HIGH. RESET must be HIGH during normal operation. RESET is CMOS rail to rail 
signal with DC high and low at 80% and 20% of VDD, example, 1.20V for DC high and 0.30V 
for DC low.

T3

A13

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

T4

NO_USE

-

Not used

T5

NO_USE

-

Not used

T6

NO_USE

-

Not used

T7

A14

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.