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68
SCD-XA333ES
Pin No.
Pin Name
I/O
Description
60
BCKAO
O
Bit clock signal (2.8224 MHz) output terminal for DSD data output Not used (open)
61
PHREFI
I
Phase reference signal input for DSD output phase modulation from the CXD9647R (IC803)
62
PHREFO
O
Phase reference signal output terminal for DSD output phase modulation Not used (open)
63
ZDFL
O
Zero data (front L-ch) flag detection signal output terminal Not used (open)
64
DSAL
O
DSD data (front L-ch) output to the CXD9647R (IC803)
65
ZDFR
O
Zero data (front R-ch) flag detection signal output terminal Not used (open)
66
DSAR
O
DSD data (front R-ch) output to the CXD9647R (IC803)
67
VDDSD0
—
Power supply terminal (+3.3V) (For DSD data output)
68
ZDFC
O
Zero data (center) flag detection signal output terminal Not used (open)
69
DSAC
O
DSD data (center) output to the CXD9647R (IC803)
70
ZDFLFE
O
Zero data (sub woofer) flag detection signal output terminal Not used (open)
71
DSALFE
O
DSD data (sub woofer) output to the CXD9647R (IC803)
72
VSDSD1
—
Ground terminal (For DSD data output)
73
ZDFLS
O
Zero data (surround L-ch) flag detection signal output terminal Not used (open)
74
DSALS
O
DSD data (surround L-ch) output to the CXD9647R (IC803)
75
ZDFRS
O
Zero data (surround R-ch) flag detection signal output terminal Not used (open)
76
DSARS
O
DSD data (surround R-ch) output to the CXD9647R (IC803)
77
VDDSD1
—
Power supply terminal (+3.3V) (For DSD data output)
78, 79
TESTO
O
Output terminal for the test (normally: open)
80
VSCB0
—
Ground terminal (for core)
81, 82
TESTO
O
Output terminal for the test (normally: open)
83
VDCB0
—
Power supply terminal (+2.5V) (for core)
84, 85
TESTO
O
Output terminal for the test (normally: open)
86
VSIOB0
—
Ground terminal (for I/O)
87
TESTO
O
Output terminal for the test (normally: open)
88, 89
TESTI
I
Input terminal for the test (normally: fixed at “L”)
90
VDIO
—
Power supply terminal (+3.3V) (for I/O)
91 to 93
TESTO
O
Output terminal for the test (normally: open)
94
VSCB1
—
Ground terminal (for core)
95 to 97
TESTI
I
Input terminal for the test (normally: fixed at “L”)
98
TESTO
O
Output terminal for the test (normally: open)
99
VDCB1
—
Power supply terminal (+2.5V) (for core)
100 to 105
TESTI
I
Input terminal for the test (normally: fixed at “L”)
106
VSIOB1
—
Ground terminal (for I/O)
107 to 109
TESTI
I
Input terminal for the test (normally: fixed at “L”)
110
VDIOB1
—
Power supply terminal (+3.3V) (for I/O)
111 to 114 WAD0 to WAD3
I
External A/D data input terminal from the A/D converter for PSP physical disc mark detection
Not used (open)
Not used (open)
115
TESTI
I
Input terminal for disc inspection mode from the I/O expander (IC902)
116
VSCB2
—
Ground terminal (for core)
117 to 120 WAD4 to WAD7
I
External A/D data input terminal from the A/D converter for PSP physical disc mark detection
Not used (open)
Not used (open)
121
VDCB2
—
Power supply terminal (+2.5V) (for core)
122
TESTI
I
Input terminal for the test (normally: fixed at “L”)
123
WCK
I
Operation clock signal input for PSP physical disc mark detection from the CXD1882R (IC701)
124, 125
WAVDD0, 1
—
A/D power supply terminal (+2.5V) (for PSP physical disc mark detection)
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