Read Sony SCD-XA333ES Service Manual online
64
SCD-XA333ES
Pin No.
Pin Name
I/O
Description
54
HINT
O
Not used (pull up)
55
XS16
O
Not used (pull up)
56
HA1
I
Not used (fixed at “H” )
57
XPDI
I/O
Not used (pull up)
58
VDDS
—
Power supply terminal (+5V) (digital system)
59, 60
HA0, HA2
I
Not used (fixed at “H” )
61
VSS
—
Ground terminal (digital system)
62, 63
HCS0, HCS1
I
Not used (open)
64
VDD
—
Power supply terminal (+3.3V) (digital system)
65
DASP
I/O
Not used (pull up)
66 to 69
MDB0 to MDB3
I/O
Two-way data bus with the D-RAM (IC706)
70
VSS
—
Ground terminal (digital system)
71
MDB4
I/O
Two-way data bus with the D-RAM (IC706)
72
VDD5V
—
Power supply terminal (+5V)
73 to 75
MDB5 to MDB7
I/O
Two-way data bus with the D-RAM (IC706)
76
XMWR
O
Write enable signal output to the D-RAM (IC706)
77
VDD
—
Power supply terminal (+3.3V) (digital system)
78
XRAS
O
Row address strobe signal output to the D-RAM (IC706)
79, 80
MA0, MA1
O
Address signal output to the D-RAM (IC706)
81
VSS
—
Ground terminal (digital system)
82 to 87
MA2 to MA7
O
Address signal output to the D-RAM (IC706)
88
VDD
—
Power supply terminal (+3.3V) (digital system)
89
MA8
O
Address signal output to the D-RAM (IC706)
90
VSS
—
Ground terminal (digital system)
91
MA9/MNT0
O
Address signal output to the D-RAM (IC706)
92
MA10/MNT1
O
RF data signal output terminal Not used (open)
93
MA11/MNT2
O
Operation clock signal output for PSP physical disc mark detection
Monitor signal output to the CPU (IC901)
Monitor signal output to the CPU (IC901)
94
XMOE
O
Output enable signal output to the D-RAM (IC706)
95
XCAS
O
Column address strobe signal output to the D-RAM (IC706)
96, 97
MDB8, MDB9
I/O
Two-way data bus with the D-RAM (IC706)
98
VSS
—
Ground terminal (digital system)
99
MDBA
I/O
Two-way data bus with the D-RAM (IC706)
100
VDD
—
Power supply terminal (+3.3V) (digital system)
101, 102
MDBB, MDBC
I/O
Two-way data bus with the D-RAM (IC706)
103
VDD5V
—
Power supply terminal (+5V)
104 to 106 MDBD to MDBF
I/O
Two-way data bus with the D-RAM (IC706)
107
GFS
O
Guard frame sync signal output to the CPU (IC901)
108
VSS
—
Ground terminal (digital system)
109
APEO
O
Absolute phase error signal output
110
VDD
—
Power supply terminal (+3.3V) (digital system)
111
DASYO
O
RF binary signal output
112
GNDA5
—
Ground terminal (analog system)
113, 114
ASF1, AFS2
—
Filter connected terminal for selection the constant asymmetry compensation
115
DASYI
I
Analog signal input after integrated from the RF binary signal
116
RFDCC
I
Input terminal for adjusting DC cut high-pass filter for RF signal Not used (open)
117
RFIN
I
RF signal input from the CXD1881R (IC001)
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