Read Sony SCD-XA333ES Service Manual online
65
SCD-XA333ES
Pin No.
Pin Name
I/O
Description
118, 119 VCCA5, VCCA4
—
Power supply terminal (+3.3V) (analog system)
120
VCOR1
—
VCO oscillating range setting resistor connected terminal
121
VCOIN
I
VCO input terminal
122, 123 GNDA4, GNDA3
—
Ground terminal (analog system)
124
LPF5
O
Signal output from the operation amplifier from PLL loop filter
125
VC1
I
Middle point voltage (+1.65V) input terminal
126, 127
LPF2, LPF1
I
Inverted signal input to the operation amplifier from PLL loop filter
128, 129 VCCA3, VCCA2
—
Power supply terminal (+3.3V) (analog system)
130
PDO
O
Signal output from the charge pump for phase comparator
131
PDHVCC
I
Middle point voltage input terminal for RF PLL
132
FDO
O
Signal output from the charge pump for frequency comparator
133, 134 GNDA2, GNDA1
—
Ground terminal (analog system)
135
SPO
O
Spindle motor (M3) control signal output to the BA5912AFP (IC512)
136
VC2
I
Middle point voltage (+1.65V) input terminal
137
MDIN2
I
Spindle motor (M3) servo drive signal input from the CXD3008Q (IC509)
138
MDIN1
I
MDP input terminal
139
VCCA1
—
Power supply terminal (+3.3V) (analog system)
140
CLVS
O
Control signal output for selection the spindle control filter at CLVS
141
VSS
—
Ground terminal (digital system)
142
MDSOUT
O
Frequency error output terminal of internal CLV circuit
143
VDD
—
Power supply terminal (+3.3V) (digital system)
144
MDPOUT
O
Phase error output terminal of internal CLV circuit
145
DEFECT
I
Defect signal input terminal Not used (fixed at “L” )
146
GSCOR
I
Guard subcode sync (S0+S1) detection signal input from the CXD3008Q (IC509)
147
EXCK
O
Subcode serial data reading clock signal output to the CXD3008Q (IC509)
148
SBIN
I
Subcode serial data input from the CXD3008Q (IC509)
149
VSS
—
Ground terminal (digital system)
150
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD3008Q (IC509)
151
WFCK
I
Write frame clock signal input from the CXD3008Q (IC509)
152
VDD5V
—
Power supply terminal (+5V)
153
XRCI
I
RAM overflow signal input terminal Not used (fixed at “L” )
154
VDDS
—
Power supply terminal (+5V) (digital system)
155
C2PO
I
C2 pointer signal input from the CXD3008Q (IC509)
156
VDD
—
Power supply terminal (+3.3V) (digital system)
157
DBCK
O
Bit clock signal (2.8224 MHz) output terminal Not used (open)
158
BCLK
I
Bit clock signal (2.8224 MHz) input from the CXD3008Q (IC509)
159
DDAT
O
PCM data output terminal Not used (open)
160
MDAT
I
Serial data input from the CXD3008Q (IC509)
161
VSS
—
Ground terminal (digital system)
162
DLRC
O
L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
163
LRCK
I
L/R sampling clock signal (44.1 kHz) input from the CXD3008Q (IC509)
164
XRST
I
Reset signal input from the I/O expander (IC902) “L”: reset
165
IFS0
I
Interface select signal input terminal Fixed at “L” in this set
166
IFS1
I
Interface select signal input terminal Fixed at “H” in this set
167
XTAL
I
33.8688 MHz clock signal input terminal
168
VSS
—
Ground terminal (digital system)
169
XTA2
O
System clock output terminal (33.8688 MHz)
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