Read Sony HCD-V5500 / MHC-V5500 / MHC-V7700AV Service Manual online
HCD-V5500
6-2.
BLOCK DIAGRAM — VIDEO SECTION —
— 15 —
— 16 —
RGB-YUV
CONV.
TIMING
GEN.
NOISE
REDUSER
YUV-RGB
CONV.
60
67
51
58
1
4
•
6
9
11
18
71
74
•
76
80
63
70
1
4
•
6
9
11
18
MEMORY
CONT.
DRAM
IF
29
30
31
98
100
97
DCLKI
Y
C
Y
C
NOISE REDUCTION
IC301
DEMPX, LEVEL
TRANSLATOR
&
INTERPOLTATOR
VIDEO
POSTPROCESSOR
&
SYNC GENERATOR
LPF
LPF
DELAY
MODULATOR
SYNC
SLOPE
GEN.
CLOSED
CAPTION
ENCODER
SIO & I
2
O-BUS
CONT.
SUB
CARRIER
GEN.
SYNC GEN.
&
TIMING CONT.
49 50
48
59 60
62
55
57
51
1/2
56
XRST
DCLK
HSYNC
VSYNC
DCLK
XVRST
FID
VSYNC
HSYNC
VDAC-XLAT
CLK
DATA
3
4
5
6
X401
27MHz
CT401
13.5MHZ
CLOCK GENARATOR
IC402
Y, C/Y, U, V
SELECTOR
&
INTER-
POLATOR
24
29
32
5
3
1
3
2
7
7
1
4
3
V
Y
C
10BIT VIDEO D/A CONVERTER
IC401
5
7
VIDEO AMP
IC451
Y/C AMP
IC452
J603
Q601
J601
IC601
SELECTOR
S VIDEO OUT
MONITOR OUT
VIDEO IN
NR-XCS
MCLK
MDATA
MDATA
MDATA
RESET
OS-XLAT
MCLK
MCLK
OUTPUT
CONT.
4
3
2
1
8
OSD
IC271
VIDEO
RAM
DATA INPUT
SHIFT
RESISTOR
SYNC
CONT.
DATA
SEL.
DISPLAY
POSITION
CONT.
18
17
16
15
19
20
OSC
1
5
CK 1/2 Q
6.75MHz
DCLK
HSYNC
VSYNC
XOSDEN
OSD R
OSD G
OSD B
CLOCK
GENERATOR
IC272
97
95
92
93
94
89
56
57
58
59
118
HSYNC
XSGRST
VSYNC
FID
DCLK
XOSDEN
XOSDEN
OSD B
OSD G
OSD R
XRST
MPEG
VIDEO
VIDEO
DECODER
MPEG
SYSTEM
DECODER
CD-ROM
DECODER
MPEG
AUDIO
DECODER
112
111
110
109
103
100
101
102
11
12
13
14
15
9
8
7
6
5
2
3
BUFFER
IC501 (1/2)
HOST INTERFACE
117
115
116
114
EACH CIRCUIT BLOCK
D-RAM INTERFACE
34
30
15
16
31
5 6
• •
•
119 120
7–13 16
•
17–21 23 24 32 33
•
•
•
•
38–43 46–55
•
X202
28.63636MHz
106
107
X201
45.1584MHz
XTL0O
XTL01
XTL2O
XTL2I
MPEG DECODER
IC201
18–21 24–28
•
27
20
22
55
2–10 21 23–25
•
•
•
2–5 7–10 35–38 40–43
•
•
LCAS
UCAS
W
RAS
A8
A0
DQ16
DQ1
WE
CE1
OE
A12
A0
I/O8
I/O1
D-RAM
IC251
S-RAM
IC751
D0
D7
A0
A3
XHCS
XWR
XHDT
XHIRQ
•
11–13 15–19
8
10
9
6
1
2
11
12
13
XTCS
IC772
41
54
56 43 70
7 8
21–29 • 31–35
13 – 20
37
35
68
49
48
47
34
35
36
37
44
18
43
1
2
3
4
5
6
72
64
CMD0
CMD1
CMD2
CMD2
CMD3
SACK
QINT
MREQ
QINT
MREQ
MDATA
MCLK
OS-XLAT
NR-XCS
73
78
74
11
10
77
76
DATA
CLK
AMUTE
AMUTE
SQCK
SUBQ
SCLK
XLT
SCLK
XLT
CMD0
CMD1
CMD2
CMD2
CMD3
SACK
QINT
MREQ
NPIN
75
71
62
48
LDON
SCOR
SENS
RESET
SENS
RESET
384FS
DATA
CLK
CLK
AMUTE
SQCK
SUBQ
SCLK
SUBQ
SCLK
XLT
LDON
SCOR
SENS
XRST
SCOR
SENS
XRST
PAL
AUTO
NTSC
S601
SYSTEM SELECT
52
51
X701
10MHz
EXTAL
XTAL
11
10
52
X901
5MHz
X2
CD-XRST
X1
VDAC-XLAT
DF-XLAT
WAIT
WR
XHIRQ
AS
A17
A18
RD
A12
A0
D7
D0
MECHA CONTROL
IC701
56
55
15
IIC INTERFACE
IC901
RESET
IIC-DATA
IIC-CLK
B
CD
SECTION
(Page 14 )
B
CD
SECTION
(Page 14 )
16
BCK
ADATA
LRCK
LRCK
C2PO
384FS
ADATA
LRCK
LRCK
BCLK
4
16
IC501
(2/2)
DATA
CLK
AMUTE
384FS
11
6
3
11
27
25
21
22
16
18
12
10
3
4
5
2
13
4
1
BUFFER
IC181
XRST
6
INPUT
PLM
D/A
CONV.
MODE
MUTE
CIRCUIT
ADATA
384FS
LRCK
BCLK
DATA
CLK
CLK
DF-XLAT
AMUTE
TIMING
CIRCUIT
CLOCK
GENERATOR
1
IIC-CLK
IIC-DATA
XRST
L CH
CD FUNC
A
MAIN
SECTION
(Page 17)
2
3
1
6
7
R CH
ACTIVE LPF
IC102
X101
33.8688MHz
DIGITAL FILTER & D/A CONVERTER
IC101
• R CH: Same as L ch
• SIGNAL PATH
• SIGNAL PATH
: VIDEO
: Y
: CHROMA
: CD
: Y
: CHROMA
: CD
Y0-Y7
C0-C7
INT
40
5
4
3
IC771
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