Read Sony HCD-V5500 / MHC-V5500 / MHC-V7700AV Service Manual online
HCD-V5500
6-1.
BLOCK DIAGRAM — CD SECTION —
SECTION 6
DIAGRAMS
— 13 —
— 14 —
APC LD
AMP
RF AMP
IC103
1
2
19
3
4
5
6
RF
SUMMING
AMP
RF FQ
AMP
FOCUS
ERROR
AMP
15
TRACKING
ERROR
AMP
13
11
10
VC
BUFFER
12
VC
VC
FOCUS/TRACKING COIL DRIVE
SPINDLE/SLED MOTOR DRIVE
SPINDLE/SLED MOTOR DRIVE
IC102
1
2
4
5
T+
T–
F+
F–
19
20
16
17
10
9
12
13
M
M102
SLED
SLED
MOTOR
M
M101
SPINDLE
MOTOR
27
26
23
24
TRACKING
COIL
FOCUS
COIL
16
RF
15
MUTE
16
8
9
4
A
C
B
D
E
F
DETECTOR
1
OPTICAL PICK-UP
BLOCK (KSS-213B/S-N)
LD
DRIVE
Q101
PD
LASER
DIODE
LD
LD
POWER
INTEGRATOR
INTE-
GRATOR
28
27
26
29
RF DC
TE
SE
FE
A/D
CONVERTER
4
6
10
8
2
100
96
ASYMMETRY
CORRECTION
CORRECTION
ASY0
RF AC
ASY1
MIX
36
MIRR
DFCT
FOK
DETECTOR
DIGITAL
PLL
EFM
DEMODULATOR
CLOCK
GENERATOR
FOK
DFCT
MIRR
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SLED
SERVO
PWM
GENERATOR
TRACKING
PWM
GENERATOR
FOCUS
PWM
GENERATOR
SLED
PWM
PWM
GENERATOR
SYNC
PROTECTOR
CLV SERVO
PROCESSOR
1B TIMS
OVERSAMPLING
FILTER
NOISE
SHAPER
TIMING
GENERATOR 1
TIMING
GENERATOR 2
DIGITAL SERVO
DIGITAL SIGNAL PROCESSOR
IC101
62
XTAL
REGISTER
DATA BUS
ERROR
CORRECTOR
D/A
DATA
PROCESSOR
79
54
MUTE
GFS
99
S STOP
+5V
S101
LIMIT
SWITCH
TFDR
TRDR
FFDR
FRDR
SRDR
SFDR
MDP
32K
RAM
ADDRESS
GENERATOR
PRIORITY
EMCODER
SERIAL/PARALLEL
PROCESSOR
PEAK
DETECTOR
SUBCODE
Q
PROCESSOR
SUBCODE
P-W
PROCESSOR
DIGITAL
OUT
70
MD2
71
DOUT
EXCK
76
SBSO
75
77
78
SUBQ
SQCK
83
SCLK
73
74
SCOR
WFCK
47
BCLK
LRCK 45
DATA
46
+5V
384BD
EXCK
SUBQ
LDON
DIGITAL
OUT
IC107
OPTICAL
SUBQ
SQCK
SCLK
ADATA
LRCK
BCLK
SCOR
86
87
88
XLT
DATA
CLK
XLT
DATA
CLK
CPU
INTERFACE
SERVO
AUTO
SEQUENCER
SENS
SENS
80
56
C2PO
SERVO
INTERFACE
MIRR
91
92
DFCT
FOK
93
81
XRST
XRST
AMUTE
39
38
C2PO
VIDEO
SECTION
B
(Page 15 )
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1
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