Read Sony CFD-E90L Service Manual online
40
CFD-E90L
Pin No.
Pin Name
I/O
Description
70
XT1
I
Sub system clock input terminal (32.768 kHz)
71
XT2
O
Sub system clock output terminal (32.768 kHz)
72
VDD
—
Power supply terminal (+3.3V)
73
VSS
—
Ground terminal
74
X1
I
Main system clock input terminal (4.19 MHz)
75
X2
O
Main system clock output terminal (4.19 MHz)
76
RST
I
System reset signal input “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
77
V-CLK
O
Serial data transfer clock signal output to the electrical volume
78
V-DATA
O
Serial data output to the electrical volume
79
BL-SLEEP
O
LCD back light sleep control signal output terminal High impedance: LCD back light sleep
Not used
Not used
80
ISS1
O
ISS 1 on/off control signal output “H”: ISS 1 on
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