Read Sharp LC-M3700 (serv.man9) Service Manual online
43
LC-M3700
LC-M3710
LC-M3710
43-1
43-2
Ë
VHiNJU26150-1Q(ASSY:IC2510)
DIGITAL AUDIO PROCESSOR
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
1
SDO2
O
Sound data output CH2
2
SDO1
O
Sound data output CH1
3
SDO0
O
Sound data output CH0
4
SDA2
I/O
I2C I/O (for download)
5
SCL/SCK
I
I2C clock / serial clock
6
SDA/SDOUT
I/O
I2C I/O / serial out
7
AD1/SDIN
I
I2C address / serial in
8
AD2/SSX
I
I2C address / serial enable
9
VDDO
—
Power supply for oscillator (+2.5V)
10
XI
I
Clock input terminal
11
XO
O
Output for VCO connection
12
VSSO
—
Oscillator power supply GND
13
RESET
I
Reset terminal
14
VDDC
—
Internal power supply +2.5V
15
VSSC
—
Internal power supply GND
16
SCL2
I/O
I2C clock output (for download)
17
VDDC
—
Internal power supply +2.5V
18
VDDC
—
Internal power supply +2.5V
19
VSSC
—
Internal power supply GND
20
VSSC
—
Internal power supply GND
21
VDDR
—
Power supply for I/O (+2.5V)
22
VDDR
—
Power supply for I/O (+2.5V)
23
VSSR
—
I/O ground
24
VSSR
—
I/O ground
25
SDI0
I
Sound data output channel 0
26
SDI1
I
S
ound data output channel 1
27
SDI2
I
S
ound data output channel 2
28
LRI
I
LR clock input
29
BCKI
I
Bit clock input
30
MCK
O
A/D, D/A clock input
31
BCKO
O
Bit clock output
32
LRO
O
LR clock output
Ë
VHiTA2024++-1Y (ASSY:IC2303)
STEREO 15W (4
Ω
) DIGITAL AUDIO AMPLIFIER
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
2,3
DCAP2,
Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square
DCAP1
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
4,9
V5D, V5A
—
Digital 5VDC, Analog 5VDC
5,8,17
AGND1,
—
Analog Ground
AGND2,
AGND3
6
REF
—
Internal reference voltage; approximately 1.0 VDC.
7
OVERLOADB
A logic low output indicates the input signal has overloaded the mplifier.
10,14
OAOUT1,
O
Input stage output pins.
OAOUT2
11,15
INV1,
Single-ended inputs. Inputs are a "virtual" ground of an inverting opamp with
INV2
approximately 2.4VDC bias.
12
MUTE
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays
in the mute mode. This pin should be tied to GND if not used.
16
BIASCAP
Input stage bias voltage (approximately 2.4VDC).
18
SLEEP
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
19
FAULT
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
20,35
PGND2,
—
Power Grounds (high current)
PGND1
22
DGND
—
Digital Ground. Connect to AGND locally (near the TA2024).
24,27,
OUTP2 & OUTM2,
O
Bridged output pairs
31,28
OUTP1 & OUTM1
25,26,
VDD2,VDD2,
Supply pins for high current H-bridges, nominally 12VDC.
29,30
VDD1,VDD1
13,21,23,
N
C
—
Not connected. Not bonded internally.
32,34
33
VDDA
—
Analog 12VDC
36
CPUMP
Charge pump output (nominally 10V above VDDA)
1
5VGEN
Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
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