Read Sharp LC-M3700 (serv.man9) Service Manual online
47
LC-M3700
LC-M3710
LC-M3710
47-1
47-2
Ë
RH-iXA312WJN1Q(MT48LC2M32B2-512K) (ASSY:IC4702,4903)
64Mb: x32 SDRAM
»
Block Diagram
»
Pin Function
Pin No
.
P
in Name
I/O
Pin Function
68
CLK
I
C
lock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
67
CKE
I
C
lock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode.
The input buffers, including CLK, are disabled during power-down and self
refresh modes, providing low standby power. CKE may be tied HIGH.
20
CS#
I
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH.
CS#provides for external bank selection on systems with multiple banks.
CS# is considered part of the command code.
17, 18, 19
WE#, CAS#,RAS#
I
Command Inputs: WE# , CAS#, and RAS# (along with CS#) define the
command being entered.
16, 71, 28, 59
DQM0-DQM3
I
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. Input data is masked
during a WRITE cycle. The output buffers are placed in a High-Z state (two-
clock latency) during a READ cycle. DQM0 corresponds to DQ0-DQ7; DQM1
corresponds to DQ8-DQ15; DQM2 corresponds to DQ16-DQ23; and DQM3
corresponds to DQ24-DQ31. DQM0-DQM3 are considered same state when
referenced as DQM.
22, 23
BA0, BA1
I
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
25-27, 60-66, 24
A0-A10.
I
Address Inputs: A0-A10 are sampled during the ACTIVE command (rowaddress
A0-A10) and READ/WRITE command (column-address A0-A7 with A10
defining auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine
if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1
(LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
2, 4, 5, 7, 8, 10,
DQ0-DQ31
I/O
Data I/O: Data bus.
11, 13,
74, 76, 77, 79,
80, 82, 83,
85, 31, 33, 34,
36, 37, 39,
40, 42, 45, 47,
48, 50, 51,
53, 54, 56
14, 21, 30, 57,
NC
—
No Connect: These pins should be left unconnected.
69,70, 73
3, 9, 35, 41, 49,
N.C.
—
DQ Power Supply: Isolated on the die for improved noise immunity.
55, 75, 81
6, 12, 32, 38,
VR4
O
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
46, 52, 78, 84
1, 15, 29, 43
VR3
O
Power Supply: +3.3V ±0.3V.
44, 58, 72, 86
N.C.
—
Ground.
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