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35
LC-M3700
LC-M3710
LC-M3710
35-1
35-2
Ë
VHiTFP501++-1Q (ASSY:IC1104)
Panel Bus HDCP DIGITAL RECEIVER
»
Block Diagram
»
Pin Function
Pin No
.
P
in Name
I/O
Pin Function
79
AGND
—
Analog ground—Ground reference and current return for analog circuitry.
79
AGND
—
Analog ground—Ground reference and current return for analog circuitry.
82,85,88,91
AVDD
—
Analog VDD—Power supply for analog circuitry. Nominally 3.3V.
67
CAP
O
Bypass capacitorÅ\4.7 _F tantalum and 0.01 _F ceramic capacitors connected to ground.
41,40
CTL[2:1]
O
General purpose control signals—Used for user defined control. In normal mode
CTL1 is not powered down via PDO.
94
DDC_SA
1
Display data channel_serial address—I2C Slave address bit A0 for display data
channel (DDC). Refer to I2C Interface section for more details.
92
DDC_SCL
I/O
Display data channel_serial clock—I2C Clock for the DDC. External pullup
resistors = 10 k_ and 3.3V to lerant.
93
DDC_SDA
I/O
Display data channel_serial data—I2C Data for the DDC. External pullup
resistors = 10 k_ and 3.3V to lerant.
46
DE
O
Output data enable—Used to indicate time of active video display versus
nonactive display or blanking interval. During blanking, only HSYNC, VSYNC
and CTL1_2 are transmitted. During times of active display, or nonblanking,
only pixel data, QE[23:0] and QO[23:0], is transmitted.
High: active display interval
Low: blanking interval
1
DFO
I
Output clock data format—Controls the output clock (ODCK) format for either
TFT or DSTN panel support. For TFT support ODCK clock runs continuously.
For DSTN support ODCK only clocks when DE is high; otherwise, ODCK is held
low when DE is low.
High: DSTN support/ODCK held low when DE = low.
Low: TFT support/ODCK runs continuously.
5, 39, 68
DGND
—
Digital ground—Ground reference and current return for digital core.
6, 38
DVDD
Digital VDD—Power supply for digital core. Nominally 3.3V.
48
HSYNC
O
H
orizontal sync output
100
OCK_INV
I
ODCK Polarity _ Selects ODCK edge on which pixel data (QE[23:0] and QO
[23:0]) and control signals(HSYNC, VSYNC, DE, CTL1_2 ) are latched.
Normal mode:
High: latches output data on rising ODCK edge.
Low: latches output data on falling ODCK edge.
44
ODCK
O
Output data clock—Pixel clock. All pixel outputs QE[23:0] and QO[23:0]
(if in 2-pixel/clock mode) along with DE, HSYNC, VSYNC and CTL[2:1] are
synchronized to this clock.
19, 28,45, 58,76
OGND
—
Output driver ground—Ground reference and current return for digital output drivers.
18, 29,43, 57,78
OVDD
—
O
utput driver VDD—Power supply for output drivers. Nominally 3.3V.
2
P
D
I
Power down—An active low signal that controls the TFP501 power-down state.
During power down all output buffers are switched to a high-impedance state
and brought low through a weak pulldown. All analog circuits are powered down
and all inputs are disabled, except for PD.
If PD is left unconnected, an internal pullup defaults the TFP501 to normal operation.
High: normal operation
Low: power down
9
PDO
I
O
utput drive power down—An active low signal that controls the power-down
state of the output drivers.
During output drive power down, the output drivers (except SCDT and CTL1) are
driven to a high-impedance state. A weak pulldown slowly pulls these outputs to
a low level. When PDO is left unconnected an internal pullup defaults the
TFP501 to normal operation.
High: normal operation/output drivers on.
Low: output drive power down.
98
PGND
—
PLL ground _ Ground reference and current return for internal PLL.
4
PIXS
I
Pixel select—Selects between one or two pixel per clock output modes. During
2-pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are
output in tandem on a given clock cycle. During 1 pixel/clock, even and odd
pixels are output sequentially, one at a time, with the even pixel first, on the
even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The
second pixel per line is pixel-1, the odd pixel.)
High: 2 pixel/clock
Low: 1 pixel/clock
95
PROM_SCL
I/O
EEPROM_serial clock—I2C clock for EEPROM interface data. External pullup
resistors = 10 k_ and 3.3V to lerant.
96
PROM_SDA
I/O
EEPROM_serial data—I2C data for EEPROM interface data. External pullup
resistors = 10 k_ and 3.3V to lerant.
97, 99
PVDD (1, 2)
PLL VDD—Power supply for internal PLL. Nominally 3.3V.
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