LC-46X8E. Major IC Informations - Sharp TV Service Manual (repair manual). Page 24

LC-46X8E/S/RU

5 – 24

53, 52

CK, CK

I

Clock: CK and CK are differential clock inputs. 
CMD, ADD inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. 
Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).

41

CKE

I

Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals and device input 
buffers and output drivers. 
Taking CKE Low provides Precharge Power-Down and Self Refresh operation(all banks idle), or Active 
Power-Down (row Active in any bank). 
CKE is synchronous for power down entry and exit, and for self refresh entry. 
CKE is asynchronous for self refresh exit. 
CKE must be maintained high throughout read and write accesses. 
Input buffers, excluding CK, CK and CKE are disabled during powerdown. 
Input buffers, excluding CKE, are disabled during self refresh.

51

CS

I

Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank 
selection on systems with multiple banks. CS is considered part of the command code.

19

ODT

I

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the gDDR2 
SDRAM. When enabled, ODT is only applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM 
signal for x16 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is pro-
grammed to disable ODT.

77, 76, 70

RAS, CAS, WE

I

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

66, 62

(L) UDM

I

Input Data Mask: DM is an input mask signal for write data. 
Input data is masked when DM is sampled HIGH coincident with that input data during a WRITE access. 
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.

42, 71

BA0 - BA1

I

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE 
command is being applied. BA0 also determines if the mode register or extended mode register is to be 
accessed during a MRS or EMRS cycle.

50, 72, 75, 
44, 49, 73, 
74, 45, 48, 
46, 43, 47, 13

A0 - A12

I

Address Inputs: Provided the row address for ACTIVE commands, and the column address and AUTO 
PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the 
respective bank. 
A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one 
bank(A10 LOW) or all banks (A10 HIGH). 
If only one bank is to be precharged, the bank is selected by BA0, BA1. 
The address inputs also provide the op-code during MODE REGISTER SET commands.

DQ

I/O

Data Input/ Output: Bi-directional data bus.

81, 57,
61, 29

LDQS, (LDQS)
UDQS, (UDQS)

I/O

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write 
data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. 
The data strobes LDQS and UDQS may be used in single ended mode or paired with optional comple-
mentary signals LDQS and UDQS to provide differential pair signaling to the system during both reads 
and writes. 
An EMRS (1) control bit enables or disables all complementary data strobe signals.

10, 14, 15, 
16, 32, 36, 

NC/RFU

—

No Connect: No internal electrical connection is present.

3, 7, 22, 24, 
26, 28, 63, 
67, 80, 84

VDDQ

—

DQ Power Supply: 1.8V 

± 0.1V.

33, 35, 37, 
39, 54, 56, 
58, 60, 82

VSSQ

—

DQ Ground.

9

VDDL

—

DLL Power Supply: 1.8V 

± 0.1V.

78

VSSL

—

DLL Ground.

5, 12, 18, 20

VDD

—

Power Supply: 1.8V 

± 0.1V.

11. 17, 65, 69 VSS

—

Ground.

40

VREF

—

Reference voltage.