LC-46X8E. Major IC Informations - Sharp TV Service Manual (repair manual). Page 20

LC-46X8E/S/RU

5 – 20

F32

MD56

I/O

Memory data bus.

DDR_DQ60

F33

MD57

I/O

Memory data bus.

DDR_DQ59

E33

MD58

I/O

Memory data bus.

DDR_DQ57

E34

MD59

I/O

Memory data bus.

DDR_DQ62

D34

DQM7

O

Memory data write mask enable for byte 7.

DDR_DM7

C33

DQS7

I/O

Data strobe for memory data bus MD[63:56].

DDR_DQS7

C34

DQS7N

I/O

Data strobe for memory data bus MD[63:56].

DDR_DQS7#

B33

MD60

I/O

Memory data bus.

DDR_DQ63

B34

MD61

I/O

Memory data bus.

DDR_DQ56

A32

MD62

I/O

Memory data bus.

DDR_DQ58

A33

MD63

I/O

Memory data bus.

DDR_DQ61

CPU Interface
B26

MASTSEL

I

Lexra bus master select, H: I2C, L: 1x5180.

R-GND

Interrupt Interface
T1

INT1

I

External interrupt, low active. Edge or level.

N_CPLD_INTO

I2C Interface
W5

SCLMAST2

I/O

I2C master 2 clock.

SCL1

Y5

SDAMAST2

I/O

I2C master 2 data.

SDA1

AE5

SCLMAST1

I/O

I2C master 1 clock.

SCL0

AF5

SDAMAST1

I/O

I2C master 1 data.

SDA0

I2S Interface
T3

SCKIN

O

I2S: SCK of I2S input port. (Not used)
AC Link: SDATA_OUT
POD2: POD_DRXB, the second POD OOB RX data.

open

T4

WSI2S

I

I2S: WS of I2S input port. (Not used)
AC Link: ACLINK_RSTN
POD2: POD_CRXB, the second POD OOB RX gapped clock.

open

T5

SDI2S

I

I2S: SD of I2S input port. (Not used)
AC Link: SYNC
POD2: POD_QTXB, the second POD OOB TXQ channel.

open

U1

WS

O

I2S: WS of I2S output port.
AC Link: SDATA_IN_2

DTV_WS

U2

SCK

O

I2S: SCK of I2S output port.
AC Link: SDATA_IN_3

DTV_SCK

U3

SD1

O

I2S: SD of I2S output port.
AC Link: BIT_CLK

DTV_SDO

U4

SD2

O

I2S: SD of I2S output port. (Not used)
AC Link: SDATA_IN_0

open

U5

SD3

O

I2S: SD of I2S output port. (Not used)
AC Link: SDATA_IN_1

open

V5

I2SCLK

O

I2S: 1, 2, 4, 8 times of SCK of I2S output port, used by D/A chip.

DACCLK

V4

SD4

I

I2S: SCK of second I2S input port. (Not used)
POD2: POD_ETXB, the second POD OOB TX enable.

open

V3

SD5

I

I2S: WS of second I2S input port. (Not used)
POD2: POD_ITXB, the second POD OOB TXI channel.

open

V2

SD6

I

I2S: SD of second I2S input port. (Not used)
POD2: POD_CTXB, the second POD OOB TX gapped symbol 
clock.

open

SPDIF Interface
T2

SPDIF

I/O

SPDIF output.

DTV_SPDIF

UART Interface
Y4

TXD

O

Data output for UART.

UATXD1_1

Y3

RTS

O

Request to send output for UART (8mA output pad).

UATXD2_1

Y2

DTR

O

Data terminal Ready output for UART (8mA output pad, 5V TTL 
interface 25PF, 6ns rise timing).

open

Y1

RXD

I

Data input for UART.

UARXD1_1

AA1

CTS

I

Clear to send input for UART.

UARXD2_1

AA2

DSR

I

Data set ready for UART.

open

AA3

DCD

I

Receive line signal detect for UART. (Not used)

open

AA4

RI

I

Ring indicator for UART. (Not used)

open

Smart card Interface
V1

SCRST

I

Smart card reset 0, 8mA open-drain output pad. (Not used)

open

W1

SCPFET

I

Smart card power FET control output, 8mA open-drain output. The 
smart card reader interface requires this pin to drive an external 
power FET to supply the current for the Smart Card (65mA typical, 
100mA short to ground). (Not used)

open