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XG-NV1U
55
Explanation of bits shown in 8-6-3.
BIT
DESCRIPTION
STTC
Status bit for horizontal time constant : LOW = TV time constant : HIGH = VCR time constant.
HLCK
Status bit for locked horizontal frequency : LOW = locked : HIGH = unlocked.
FIDT
Identification bit for detected field frequency : LOW = 50 Hz : HIGH = 60 Hz.
GLIM
Gain value for active luminance is limited (maximum or minimum), active HIGH.
XXX
reserved
WIPA
White peak loop is activated, active HIGH.
ALTO
Status HIGH : line alternating colour burst has been detected (PAL or SECAM).
CODE
Status HIGH : any colour signal has been detected.
8-7. I
2
C-Bus Detall
The I
2
C-bus receiver slave address is 9CH/9EH.
DMSD-SQP slave receiver (SU 00H to 19H).
8-7-1. Subaddress 00 (DATA BYTE 007 to 000)
Increment delay IDEL
-1
-4
1
1
1
1
1
1
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-195
-780
0
0
1
1
1
1
0
1
max, value for 60 Hz
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-236
-944
0
0
0
1
0
1
0
0
max,value for 50 Hz
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-256
-1024
0
0
0
0
0
0
0
0
outside central counter
(2)
DECIMAL
DELAY TIME
MULTIPLIER
(STEP SIZE = 4/LLC)
CONTROL BITS
(1)
IDEL7
IDEL6
IDEL5
IDEL4
IDEL3
ODEL2
IDEL1
IDEL0
Notes:
1. A sigh bit, designated A08 and internally set to HIGH, indicates are always negative.
2. Thwe horizontal PLL does not operate in this condition. The system clock frequency is to a value fixed by
2. Thwe horizontal PLL does not operate in this condition. The system clock frequency is to a value fixed by
the last update and is within ±7.1% of the nominal frequency.
DECIMAL
DELAY TIME
MULTIPLIER
(STEP SIZE = 2/LLC)
CONTROL BITS
HSYB7 HSYB6 HSYB5 HSYB4 HSYB3 HSYB2 HSYB1 HSYB0
8-7-2. Subaddress 01 (DATA BYTE 015 to 008)
Horizontal synchronization begin 50 Hz (HSYB)
+191
-382
1
0
1
1
1
1
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-64
+128
1
1
0
0
0
0
0
0
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