XG-NV1E (serv.man18). Technical manual - Sharp Projector Service Manual (repair manual)

Service Headquarters:   Sharp Plaza,   Mahwah,   New Jersey 07430-2135

335 Britannia Road East Mississauga,  Ontario L4Z 1W9 Canada

T37X2XGNV1U//

1. TURNING ON THE XG-NV1U ........................ 2

1-1. No need to switch on the set ................... 2
1-2. Power-on sequence ................................ 2
1-3. Micro processor

(IC5001: RH-iX2961CEZZ) ..................... 3

1-4. 8-bit 12-ch D/A converter (M62352GP) ... 6
1-5. Terminal Functions (IC5002: TE9752) ... 10

2. SIGNAL PROCESSING CIRCUIT ................ 13

2-1. Block Diagram ....................................... 13
2-2. STG (Signal Timing Generator) ............. 14
2-3. SVP (Signal Video Processor) .............. 17
2-4. Concept of electronic zoom

signal processing .................................. 18

2-5. DGA IC Block Diagram ......................... 20

3. OUTPUT CIRCUIT ....................................... 21

3-1. 6-ch Divider Drive Circuit ....................... 21
3-2. Signal Processing Section ..................... 25
3-3. Feedback Circuit ................................... 26
3-4. White Voltage and

Black Voltage Generator Circuit ............ 27

4. PC (Personal Computer) CONTROL ............ 28

4-1. Transfer Conditions ............................... 28

4-2. Basic Format ......................................... 28
4-3. Pin Connections Block Diagram ............ 28

5. MOUSE CONTROL ...................................... 29

5-1. Block Diagram ....................................... 29
5-2. Pin Functions ........................................ 29
5-3. Mouse Interface Specifications ............. 31

6. POWER/BALLAST ....................................... 35

6-1. Difference From Conventional Circuits .. 35

7. VIDEO UNIT .................................................. 36

7-1. Video Unit General Layout .................... 37

8. ONE CHIP FRONT-END1

(OCF1)(IC6001: SAA7110(A)) ...................... 38
8-1. Features ................................................. 38
8-2. Block Diagram ....................................... 39
8-3. Pinning ................................................... 40
8-4. Typical Pin Layout ................................. 43
8-5. Functional Description ........................... 44
8-6. I

2

C-Bus Receiver/Transmitter Tables ..... 52

8-7. I

2

C-Bus Detail ........................................ 55

8-8. I

2

C-Bus Detauk (Continued) .................. 63

8-9. I

2

C-Bus Start Set-Up ............................. 73

Page

Page

Turn on the AC power, and the backup power supply is activated to feed DC power. Then the IC5001 microprocessor
(IX2961CE) is turned on and initialized.

This set is on/off-controlled by the microprocessor. The microprocessor is on power when pin (54) of P-CON1 is at
the high level and pin (57) of P-CON2 at the low level.

If the pins are not at their respective levels, there must be something wrong with the microprocessor. First check the
system clock. Make sure the clock is applied to pins (74 ) and (75). Then check the interruption port. Make sure pins
(1), (2), (3), (4) and (77) are kept at the low level. Now check to see if the address bus and data bus are properly
connected with the IC5003 program circuit (IX2964CE). The IC5003 pins correspond to the IC socket pins.

Check the B power line.

1. The AC power switch is turned on.
2. The primary power circuit (RDENC0227CEZZ) is activated.
3. A voltage is given out to the EA connector (6V backup voltage fed to pin (5)).
4. The backup circuitry (composed of IC5001, IC5002, IC5003, IC5005, IC5006, IC5007, and IC5010) is activated.
5. The IC5001 microprocessor is initialized first and then the IC5002 is also initialized.
6. The data is read out of the IC5010 EEPROM.
7. Pin (54) of P-CON1 of IC5001 gets to the high level. The chassis and fan get started.
8. The DAC M62352GP data is set on the IC4034, IC305 and IC1012.
9. The video board (RUNTK0567CEZZ) is checked. The IIC bus at pins (55)(SDA) and (56)(SCL), both on the IC5001,

are used to make sure that the board exists.

10.The gate array is cleared (when pin (82)(UGRESN) of IC5002 gets from the low to the high level).
11. All the ICs are initialized. Because of the 3-wire bus design, the microprocessor works to send the data only.
12.Pin (57) of P-CON2 of IC5001 gets to the high level. The lamp lights up.
13.Now the set gets started.

1

NMI

INDEX

IMT0
IMT1
IMT2

ST

A0
A1
A2
A3

Vss

A4
A5
A6
A7
A8
A9

A10
A11
A12
A13
A14

A15
A16
A17

2
3
4
5
6
7

8
9
10
11

12
13

14
15
16
17
18

19
20
21
22

23
24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

67

68

69

70

71

72

73

74

75

76

77

78

79

80

66

A18

A19

D0

D1

D2

D3

D4

D5

D6

D7

Vss

PG0/AN0

PG1/AN1

TOUT1

Vcc

Vss

PG2/AN2

PG3/AN3

PG4/AN4

PG5/AN5

RTS0

CTS0

DCD0

TXA0

RXA0

CKA0/DREQ0

TOUT2

TOUT3

IC

TXA1/PA0

RXA1/PA1

CKA1/TEND0/PA2

TXS/PA3

RXS/CTS1/PA4

CKS/PA5

DREQ1/PA6

TEND1/PA7

HALT

REF

IOE

ME

E

LIR

WR

RD

Vss

MP1

MP0

XTAL

EXTAL

Vcc

WAIT

BUSACK

BUSREQ

RESET

Ø

(FP-80B)

Ø

Timing

Generator

Bus  State  Control

Address  Bus  (16 bit)

Data

Bus

(8 bit)

CPU

Interrupt

DMAC

(2ch)

RAM

(512B)

16  bit
Reload
Timer
(2ch)

16  bit

Programable

Timer

DATA

Buffer

8

20

Address
Buffer

MMU

Analog

Comparator

(6ch)

ASCI

(channel  0)

ASCI

(channel  1)

Clocked
Serial
I/O  Port

P
O
 r
 t
G

P
O
 r
 t
A

TOUT2

TOUT3

IC

D

0

-D

7

A

0

-A

19

PG

5

-AN

5

PG

4

-AN

4

PG

3

-AN

3

PG

2

-AN

2

PG

1

-AN

1

PG

0

-AN

0

PA

6

/DREQ

1

PA

7

/TEND

1

CKA

0

/DREQ

0

PA

0

/TXA

1

PA

2

/CKA

1

/TEND

0

TOUT1

TXA

0

RXA

0

RTS

0

CTS

0

DCD

0

PA

4

/RXS

/CTS

1

PA

1

/RXA

1

PA

5

/CKS

PA

3

/TXS

XTAL

EXTAL

MP

0

MP

1

ST

BUSREQ

BUSACK

WAIT

RESET

HALT

REF

IOE

ME

E

LIR

WR

RD

NMI

INT

0

INT

1

INT

2