AR-P16 (serv.man3). Service manual - Sharp Copying Equipment Service Manual (repair manual). Page 4

AR-P16  SPECIFICATIONS  2 - 1

IBM PC/AT (Include compatible machine)

PCL

Windows 95/98/Me

Windows NT4.0 / Windows 2000 / Windows XP 
(Whistler)

WHQL

Printer driver certification

PDL

PCL5e

Support 
channel

IEEE1284 parallel port (ECP compatible)
PSERVER/RPRINT NETWARE
LPR/LPD
FTP
Net BEUI
IPP (Ver.1.0)
USB (1 port)

IEEE parallel 
port

Print data received through IEEE1284 parallel 
port
Nibble mode (PnP support), ECPcompatible

PSERVER/
RPRINT 
NETWARE

PSERVER/RPRINT mode can be used under the 
Net Ware environment.

LPR/LPD

UNIX LPR/LPD command compatible

IPP

IPP Ver.1.0 compatible

FTP

The function to print data received through the 
built-in FTP server must be provided.

Net BEUI

Microsoft NetBEUI compatible

USB

USB1.1 support
PnP support

IEEE1394

N/A

Blue Tooth

N/A

SNMP

Supports Host Resource MIB v2, Finisher MIB/
Printer MIB, and SHARP Corporate MIB.

ARP/RARP/
BOOTP/DHCP

Allows IP address assignment by ARP/RARP/
BOOTP/DCHP.

Novell 
Pconsole

Supports device monitoring by Novell Pconsole 
NW Admin.
Requires installation of a print server card. 

Novell NLSP

Supports IPC address assignment conforming to 
NLSP.
Requires installation of a print server card.

Web remote 
setup

By use of the network interface, E-mail setup, 
telephone directory setup, and network setup can 
be adjusted.

E-mail Alert/
Status

Valid only when NIC is installed. Realizes 
information in the machine as one-direction mail 
transmission function using SMTP protocol.

E-mail 
Diagnosis

The detailed information of machine is attached to 
E-mail Status/Alert.
Standard function of the controller (with NIC).

NJR v2 (Notify 
Job Result)

Sends job complete or error status.
Must conform to Sharp status monitor.

Item

Specification

CPU

• Motorola MPC755-300MHz
• Input Clock: 66MHz from MPC107
• 60x Bus (64bit Bus Width)
• Big Endian
• 32KB I Cache & 32KB D Cache
• L2 Cache I/F support (Up to 1MB)
• Package: 25mm x 25mm 360pin PBGA

System 
Controller

• Motorola MPC107-66MHz
• Input Clock: 16.345MHz from XTAL
• 60x Bus (64bit Bus Width) support
• Memory Control (SDRAM, Flash ROM)
• PCI Bus Rev. 2.1 Host Bridge Controller (33/

66MHz 32bit)

• PCI Bus Arbiter (Up to 5 masters)
• Clock Generator
• I2C Control
• 2 channels DMA support
• Interrupt Control
• Package: 33mm x 33mm 503pin PBGA

Video 
Controller ASIC

• Destiny D8501A
• Input Clock: 66MHz from MPC107
• 60x Bus (64bit Bus Width) support
• 5 channels I/O DMA support
• Local I/O Bus (32bit) Control
• 4 channels (CMYK) parallel/serial video output 

support

• IEEE 1284 I/F Control with DMA (Compatible, 

Nibble, ECP)

• Package: 456pin BGA

L2 Cache

• Not Used

SDRAM

• On Board 128MB
• Data Bus Width: 64bit
• Clock: 66MHz
• 256Mbit device (x16bit, 4banks) x 4pcs
• Assigned only CS0 in MPC107 Memory Control

SDRAM DIMM

• JEDEC Standard 168pin SDRAM DIMM x 

2slots

• 128MB or 256MB DIMM (PC100 or higher) 

support

• Assigned CS1-2 in MPC107 Memory Control 

for DIMM Slot #0

• Assigned CS3-4 in MPC107 Memory Control 

for DIMM Slot #1

• Up to 512MB (256MB x 2slot)
• SPD configuration by MPC107 I2C Control (ID 

= 4, 5)

Flash ROM 
(Boot)

• Sharp proprietary 72pin SO-DIMM
• SO-DIMM Connector: DDK DMM2-SD72B-

1131

• 8Mbit Flash chip (Sharp LH28F800BVE-TTL90 

x 1pcs  OR LH28F800BJE-PTTL90 x 1pcs)

• Assigned MPC107 RCS0 (1MB) for Boot (CN3)
• Data Bus Width: 8bit
• Flash /RP (Reset/Power-Down) pin is 

connected to a CPU reset signal

• Flash Write Protect pin and VCCW pin 

controlled by Jumper (JP1)

• Flash RD/BY (Ready/Busy) status pin is 

monitored by D8501A GPIO12