Read Sharp UP-3500 (serv.man29) Service Manual online
UP-3500 (V)
CIRCUIT DIAGRAM
– 42 –
to JTAG CN
FPGA GPIO & Serial i/f
to MCR i/f CN
Serial i/f (3/3)
cf. FPGA-section2
Serial i/f
(2/3)
(2)#A4K
(2)#A4K
(2)#A4K
(2)#A4K
(2)#A4K
cf. FPGA-section1
Serial i/f
(1/3)
PLACE
NE
A
R
F
P
G
A
P
O
W
E
R
PIN
PLACE FPGA NEAR CPU-SUB CO
N
N
E
C
T
OR
P
L
A
C
E
N
EAR F
P
GA POWER PI
N
CONNECT DCK FROM MAIN-SUB CONNECTOR
WITH MINIMUM LENGTH
2KP2QTV0COGUK
IPCN0COG
(2)#A)2+1,
#5
/56'2
(2)#A)2+1,
&5
/56'2
(2)#A)2+14
#5
/56'2
(2)#A)2+14
&5
/56'2
(2)#A)2+1
,/161((
(2)#A)2+1
4/161((
(2)#A)2+1
,/16%72
(2)#A)2+1
4/16%72
(2)#A)2+1
,2'5
(2)#A)2+1
42'5
(2)#A)2+1
2*725
(2)#A)2+1
#%7659
(2)#A)2+1
&49505
(2)#A)2+1
0
QV7
UG
(2)#A)2+1
0
QV7
UG
(2)#A)2+1
0
QV7
UG
(2)#A)2+1
8*%1/
(2)#A)2+1
564$
(2)#A)2+1
564$
(2)#A)2+1
564$
(2)#A)2+1
564$
(2)#A)2+1
#%76
(2)#A)2+1
#%76
(2)#A)2+1
&4#9'4
(2)#A)2+1
&4#9'4
(2)#A)2+124+06'
4A5'0514A10
(2)#A)2+1
+08210
(2)#A)2+1
0
QV7
UG
(2)#A)2+1
0
QV7
UG
(2)#A)2+1
0
QV7
UG
(2)#A)2+1
0
QV7
UG
(2)#A)2+1
0
QV7
UG
DTC123EKA
3
1
2 BE
C
modified 07,06,09
modified 07,06,09
FPGA_SIN5
JAS/MSTEP1
JDS/MSTEP2
RAS/MSTEP3
RDS/MSTEP4
JMOTOFF
RMOTOFF
JMOTCUP
RMOTCUP
JPES#
RPES#
PHUPS
ACUTSW
VHCOM
STRB1#
STRB3#
STRB4#
ACUT1
ACUT2
PSENSON
FPGA_SIN4
FPGA_SIN3
FPGA_SIN2
FPGA_SIN1
GPIO14
GPIO15
GPIO16
LED_PWR
GPIO30
GPIO29
GPIO31
GPIO32
GPIO14
GPIO15
GPIO16
LED_PWR
JPES#
RPES#
STRB1#
STRB2#
STRB3#
STRB4#
ACUT1
ACUT2
JAS/MSTEP1
JDS/MSTEP2
RAS/MSTEP3
RDS/MSTEP4
JMOTCUP
RMOTCUP
VHCOM
PSENSON
INVPON
JMOTOFF
RMOTOFF
GPIO32
GPIO31
GPIO29
GPIO30
FPGA_SIN6
STRB2#
TCK
MS-FLASH_TDI
TDI
FPGA_RDD1#
DCK
FPGA_DTR1
FPGA_SIN1
FPGA_SOUT1
FPGA_DSR1
FPGA_CTS1
FPGA_DCD1
FPGA_RTS1
FPGA_DTR2
FPGA_SIN2
FPGA_SOUT2
FPGA_DSR2
FPGA_CTS2
FPGA_DCD2
FPGA_RTS2
FPGA_DTR3
FPGA_SIN3
FPGA_SOUT3
FPGA_DSR3
FPGA_CTS3
FPGA_DCD3
FPGA_RTS3
FPGA_DTR4
FPGA_SIN4
FPGA_SOUT4
FPGA_DSR4
FPGA_CTS4
FPGA_DCD4
FPGA_RTS4
FPGA_DTR5
FPGA_SIN5
FPGA_SOUT5
FPGA_DSR5
FPGA_CTS5
FPGA_DCD5
FPGA_RTS5
FPGA_RCVDT2#
FPGA_RCVDT1#
FPGA_RCVDT5#
FPGA_RCVDT4#
FPGA_RCVDT3#
CKDC_SRES#
DRAWER1
DRAWER2
FPGA_DRWSNS
INVPON
FLASH_RESET#
3.3V
3.3V
1.2V
2.5V
PROG_B
FPGA_CTS6
FPGA_DCD6
FPGA_DSR6
FPGA_RCVDT6#
FPGA_RI6
FPGA_SIN6
FPGA_DTR6
LED_PWR
FPGA_RCVDT6#
2.5V
1.2V
3.3V
2.5V
2.5V
1.2V
3.3V
3.3V
3.3V
2.5V
1.2V
3.3V
2.5V
3.3V
3.3V
3.3V
3.3V
3.3V
1.2V
R82
10
K
C42
0.1uF
R86
10
K
R101
10
K
R105
(10K)
R74
4.7K
R80
10
K
2
1
3
R410
0
R92
10
K
C40
0.1uF
IC6C SN74LV00APW
9
10
8
R106
10
K
R107
10K
R273
0(UP-810F)
R73
4.7K
C41
0.1uF
R69
0
R79
10
K
U1-4
XC3S25
0
E
-P
Q
2
0
8
157
158
159
161
162
163
164
165
167
168
169
171
172
174
175
177
178
179
180
181
183
184
185
186
187
189
190
192
193
194
196
197
199
200
202
203
204
205
206
207
160
166
170
173
176
182
188
191
195
198
201
208
TDO
TCK
RDD1
DCD5
RTS5
CTS5
DSR5
SIN5
DTR5
SOUT5
CTS4
RTS4
DCD4
DSR4
SIN4
CLK
DTR4
SOUT4
DCD3
RTS3
DSR3
SIN3
DTR3
SOUT3
DCD2
RTS2
CTS2
DTR2
DSR2
SIN2
SOUT2
DCD1
RTS1
CTS1
DTR1
DSR1
SIN1
SOUT1
HSWAP
TDI
CTS3
VCCAUX
VCCINT
GND
VCCO
GND
GND
VCCO
VCCAUX
GND
VCCO
GND
R99
10
K
R77
0
R104
10
K
2
1
3
C7
100pF
R75
(4.7K)
R134
10
K
R85
10
K
R81
10
K
R94
10
K
R83
10
K
R71
10K
C15
100pF
R272
0(UP-800F)
R160
10
K
R100
10
K
R270
0(UP-820N)
R97
10
K
R89
10
K
C39
0.1uF
U1-3
X
C
3
S
2
5
0
E-PQ208
1
2
3
4
5
8
9
11
12
15
16
18
19
22
23
24
25
28
29
30
31
33
34
35
36
39
40
41
42
47
48
49
50
6
7
10
13
14
17
20
21
26
27
32
37
38
43
44
45
46
51
52
PROG_B
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
N.U.(INPUT)
VCCAUX
GND
VCCINT
N.U.(INPUT)
GND
N.U.(INPUT)
VCCO
N.U.(INPUT)
GND
N.U.(INPUT)
GND
VCCO
N.U.(INPUT)
VCCAUX
N.U.( I/O )
VCCO
N.U.(INPUT)
GND
R95
10
K
C37
0.1uF
R84
10
K
R90
10
K
R93
10
K
R91
10
K
R271
0(UP-820F)
C36
0.1uF
R96
(10K)
R103
10
K
R76
0
C38
10uF/10V
R72
0
R88
10
K
R98
10K
R102
10
K
R78
0
IC6D
SN74LV00APW
12
13
11
R87
10
K
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
4/16
FPGA-2 (GPIO
,SERIAL-I/F)
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