Read Sharp UP-3500 (serv.man29) Service Manual online
UP-3500 (V)
CIRCUIT DIAGRAM
– 41 –
JTAG
Connector
тL
2.5V
уM
(2)#OQFGUGV(
2
)
#
O
Q
F
G
U
G
V
/=?/
=
?
3-2Low
1-2High
FPGA Host & ROM i/f
Serial i/f (3/3)
to MCR CN
to JTAG CN
FPGA mode
FPGA Reset
Serial i/f (2/3)
TO CPU PWB
TO CPU PWB
SERIAL DATA INPUT FOR TIMMER START
CKIO:CONNECT FLASH MEMORY & FPGA
WITH MINIMUM PATH & STRAIGHT PATTERN
M2 M1
M
0
000 SERI
AL
M
AST
ER
011 BPI
ADDRESS DECL.
M
O
D
E
PLACE NEA
R FPGA POW
E
R
PIN
PLACE NEAR
FPGA POW
E
R P
IN
SERIAL FLASH MEMORY&JTAG CON : PLACE NEAR FPGA!!!
PLACE NE
AR
FP
GA!!
!
PLACE FPGA NEAR CPU-SUB CO
N
N
E
C
TOR
modified 07,06,09
modified 07,06,09
modified 07,06,09
modified 07,06,09
modified 07,12,26
TDO
TM
S
IO_A21
IO_A20
IO_A19
IO_A18
IO_A17
IO_A16
IO_A15
IO_A14
IO_A13
IO_A12
IO_A11
IO_A10
IO_A9
IO_A8
IO_A7
IO_A6
IO_A5
IO_A4
IO_A3
IO_A2
IO_A1
TM
S
INIT_B
TM
S
TCK
INIT_B
IO_D0
DONE
TDO
IO_A21
IO_A20
IO_A19
IO_A18
IO_A17
FPGA_M1
FPGA_M0
FPGA_M2
IO_D6
IO_D1
IO_D0
IO_D7
IO_D5
IO_D3
IO_D2
IO_D15
IO_D4
KRQ#
LANINT#
FPGA_M2
FPGA_M1
FPGA_M0
IO_D15
CCLK
DONE#
TDI
TCK
FPGA_RCP3#
FPGA_RCP2#
FPGA_RCP1#
FPGA_CLS3#
FPGA_CLS2#
FPGA_CLS1#
FPGA_RDD3#
FPGA_RDD2#
IO_A[1:21]
BYTE#
MS-FLASH_TDI
DONE
RESET#
FPGA_Ri3
FPGA_Ri2
FPGA_Ri1
FPGA_Ri4
FPGA_Ri5
FPGA_RCVDT3#
FPGA_RCVDT2#
FPGA_RCVDT1#
FPGA_RCVDT4#
FPGA_RCVDT5#
IO_D[0:15]
FPGA_OE#
FPGA_WE#
FPGA_CE#
KRQ#
LANINT#
FPGACS#
IO_RD#
IO_WE0#
FPGAINT#
A0
CKDC_SHEN#
2.5V
1.2V
3.3V
MCRINT
3
PROG_B
FPGA_RTS6
FPGA_SOUT6
DONE#
3.3V
2.5V
2.5V
1.2V
3.3V
3.3V
2.5V
1.2V
3.3V
2.5V
3.3V
3.3V
2.5V
3.3V
1.2V
3.3V
2.5V
1.2V
3.3V
2.5V
2.5V
3.3V
3.3V
C6
100pF
C33
0.1uF
R416
10
0
IC6B
SN74LV00APW
4
5
6
R60
0
C5
0.1uF
R274
1k
SP2
SHORT PIN & SOCKET
1
3
2
R53
0
U1-2
XC3S25
0
E
-P
Q
2
0
8
54
55
56
57
58
60
61
63
74
75
76
77
78
80
81
82
83
84
86
87
90
93
94
96
97
99
100
101
102
103
104
53
59
62
64
65
66
67
68
69
70
71
72
73
79
85
88
89
91
92
95
98
CS5#
CSO_B
INIT_B
WR#
RD#
BUSY
CSI_B
RESET#
D7
D6
D5
D4
D3
RDWR_B
M2
D2
D1
M1
M0
D0
FIRQ#
A23
A22
A21
A20
A19
A18
EXINT4#
A17
CCLK
DONE
GND
VCCO
RI5
RI4
RI3
VCCAUX
VCCINT
RI2
RI1
GND
N.U.(INPUT)
N.U.(INPUT)
VCCO
GND
GND
VCCO
N.U.( I/O )
N.U.(INPUT)
VCCAUX
GND
N.U.( I/O )
IC6A
SN74LV00APW
1
2
3
14
7
U2
(XCF02S(TS
S
O
P
))
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
D0
(NC)
CLK
TDI
TMS
TCK
CF#
OE/RESET#
(NC)
CE#
GND
(NC)
CEO#
(NC)
(NC)
(NC)
TDO
VCCINT
VCCO
VCCJ
U1-1
XC3S25
0
E
-P
Q
2
0
8
106
107
108
109
110
112
113
115
116
119
120
122
123
124
126
127
128
129
130
132
133
134
135
136
137
138
139
140
142
144
145
146
147
148
150
151
152
153
154
155
105
111
114
117
118
121
125
131
141
143
149
156
A16
A15
A14
A13
EXINT3#
EXINT2#
EXINT1#
RCVDT5#
RCVDT4#
A12
A11
RCVDT3#
RCVDT2#
RCVDT1#
A10
A9
A8
A7
CLS3
A6
A5
A4
A3
RCP3
A2
A1
RDD3
A0
CLS2
RCP2
RDD2
MCRINT_N#
MCRINT
CLS1
HDC
LDC0
LDC1
LDC2
RCP1
TMS
GND
VCCAUX
VCCO
VCCINT
FPGA_A0
GND
VCCO
GND
GND
VCCO
VCCAUX
GND
R42
10
K
C29
0.1uF
R50
4.7K
R40
10
K
SP1
SHORT PIN & SOCKET
1
3
2
C195
100pF
R41
10
K
(8
7831-14(M
O
LEX
))
CN6
14
12
10
8
6
4
2
13
11
9
7
5
3
1
NC
NC
TDI
TDO
TCK
TMS
VREF
GND
GND
GND
GND(CUT)
GND
GND
GND
C30
0.1uF
R51
4.7K
R58
4.7K
R55
0
D40
1SR159-200
1
2
R44
10K
C27
0.1uF
R48
10K
R59
4.7K
C35
0.1uF
C31
10uF/10V
R45
10K
C32
0.1uF
C34
0.1uF
R47
33
R56
330
R43
10
K
R54
0
C28
10uF/10V
R52
0
C26
0.1uF
A
B
C
D
87
65
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
87
65
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
87
65
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
87
65
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
3/16
FPGA-1 (R
OM,
HOST
-I/F)
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